Real Intent at DVCon 2016: Verification Solutions and Roses in Booth #802, and a Dynamic Panel Discussion about the Future of Verification

SUNNYVALE, CALIF — Feb. 22, 2016

– Who

Real Intent, the leading provider of EDA software that accelerates Early Functional Verification and Advanced Sign-off of digital designs.

– What

Will feature its Ascent and Meridian products in Booth #802 at the 2016 Design & Verification Conference & Exhibition (DVCon 2016) next week, where visitors also will receive Real Intent’s hallmark roses. In addition, Real Intent’s CTO Pranav Ashar will participate in a lively panel discussion on Wednesday, Mar. 2 organized by Real Intent: Emulation + Static Verification Will Replace Simulation. Pranav and verification experts from Imagination Technologies, Google, Cavium, Dialog Semiconductor and an industry consultant, will explore and debate the verification paradigm of the future and its impact on RTL simulation. The panel will be moderated by Jim Hogan, managing partner of Vista Ventures. Real Intent’s best-in-class products improve design team QoR and productivity, and eliminate complex failure modes of SoCs. Of special interest this year in Booth #802 is Real Intent’s iDebug state-of-the-art design intent debugger and analysis manager. It helps design engineers more easily understand and fix critical RTL and gate-level design issues such as clock-domain crossing (CDC), X-propagation and functional problems, resulting in higher-quality designs.

– When/Where

Exhibit Booth #802

Monday, Feb. 29 5 — 7pm (DVCon Booth Crawl with food and drink provided)
Tuesday, Mar. 1 2:30 —6pm
Wednesday, Mar. 2 2:30 — 6pm

– Panel Discussion — Emulation + Static Verification Will Replace Simulation

Wednesday, Mar. 2 1:30 — 2:30pm | Oak/Fir Room

Doubletree Hotel
2050 Gateway Place
San Jose, CA 95110

DVCon, which typically attracts more than 800 attendees, continues to be the premier industry conference for design and verification engineers of all experience levels, and for engineering managers. This year’s conference has expanded from the general ” Design and Verification” focus to a more specific focus on hot topic areas including: System Level Design; SoC Verification & Validation; IP Reuse and Design Automation; Mixed-Signal Design and Verification; and Lower Power Design and Verification. Conference sponsor Accellera Systems Initiative is an independent, not-for profit organization dedicated to create, support, promote, and advance system-level design, modeling, and verification standards for use by the worldwide electronics industry.

About Real Intent

Companies worldwide rely on Real Intent’s EDA software to accelerate early functional verification and advanced sign-off of electronic designs. Real Intent’s comprehensive CDC verification, advanced RTL analysis and sign-off solutions eliminate complex failure modes of SoCs, and lead the market in performance, capacity, accuracy and completeness. Please for more information.

Real Intent and the Real Intent logo are registered trademarks, and Ascent, Meridian and iDebug are trademarks of Real Intent, Inc. All other trademarks and trade names are the property of their respective owners.


CDC: Clock Domain Crossing
EDA: Electronic Design Automation
QoR: Quality of Results
RTL: Register Transfer Level
SoCs: Systems on Chip
VHDL: VHSIC High-level Design Language
VLSI: Very-Large-Scale Integration