Meridian CDC – Clock Domain Crossing
Clock Domain Crossing Sign-off
Meridian CDC is the fastest, highest capacity and most precise solution in the market for clock domain crossing (CDC) sign off. It performs comprehensive structural and functional analysis to ensure that signals crossing asynchronous clock domains in ASIC or FPGA devices are received reliably.
Designs now commonly have tens to hundreds of asynchronous clock domains. As a result, clock domain crossing verification is a critical aspect of verification sign off methodology.
Meridian CDC enables all aspects of CDC sign-off, including identifying issues related to metastability, loss of correlation, and glitch propagation.
Real Intent also offers Verix Multimode CDC, which provides the benefits of Meridian CDC and can cover all possible clocking scenarios in a single run.
CDC bugs result from a combination of poor implementation, clock timing, and analog-like behavior in digital logic. For example, if a signal crossing from one domain to another relatively asynchronous domain arrives too close to the receiving clock edge, the captured value is nondeterministic and leads to signal metastability.
The resulting errors are nearly impossible to detect and diagnose via simulation or in the lab, and cause frequent failures in the field that are expensive to fix.
High Precision, Low Noise Results
Meridian CDC is the most precise solution in the market for clock domain crossing sign off.
Its proprietary static algorithms accurately interpret and deeply analyze clock domain crossing design structures. The tool then categorizes the CDC paths into safe and unsafe paths.
This results in high precision, low noise results — even for the most complex CDC designs.
Loss of Data
Loss of Correlation
Comprehensive CDC Sign-off
Clock domain crossings can also introduce other catastrophic failures in the design. For example, they can cause loss of correlation and glitch propagation problems.
Meridian CDC comprehensively analyses clock/reset structures and identifies all possible clock domain crossing issues. These include incorrect or missing synchronization, glitch potential, reconvergence, structurally unsafe crossings, and potential data/control crossings that need functional verification.
Meridian CDC supports Verilog, VHDL, and System Verilog languages and standard SDC or TCL formats for design constraints.
Smart Reporting and Powerful GUI
Meridian CDC’s smart reporting and organization enables users to efficiently focus on their designs most critical issues, regardless of the SOC complexity.
The tool provides helpful guidance, suggesting actions to help users to quickly pinpoint the problems sources. Real Intent’s design-intent debugger and analysis manager iDebug allows user configurability and programmability with its command line interface.
Meridian CDC also includes an integrated visualization tool; it has pruned schematic views that focus precisely on fault-related logic. It then directs users to related problematic RTL-source code within a few mouse clicks. This debug approach allows for easy investigation deep into complex designs to isolate the root cause for any reported warning or error.
Real Intent iDebug customized reporting for clock domain crossing warning
Hierarchical CDC reduces the # of violations found at the chip level
Hierarchical CDC Methodology
Meridian CDC’s hierarchical capability allows users to perform clock domain crossing verification on billion-gate SOCs within a matter of hours.
The hierarchical flow is founded on a unique transparent hierarchical model derived from block-level CDC analyses, and can be used at the chip level. This unique model provides unprecedented productivity gains with flat CDC accuracy.
As a result, it delivers seamless hierarchical debug which is equivalent in accuracy to a flat run.
Dynamic CDC Verification during Simulation
Meridian CDC’s unique Simportal capability generates dynamic CDC verification models which can be compiled into a user’s simulation environment to further fortify CDC sign off. The dynamic CDC verification models include metastability injection as well as functional checks.
These models help uncover parts of the design that are not robustly protected against metastability effects. The functional check models help improve coverage on CDC signals, as well as uncover protocol inconsistencies and functional defects.
Meridian CDC Key Features for Clock Domain Crossing Sign Off
- Automatically captures design environment from design or SDC constraints
- Comprehensive clock-intent inference and analysis catches clock & reset issues
- Metastability-aware formal analysis verifies control & data stability
- Flexible top-down and bottom-up hierarchical analysis accommodates different design methodologies
Multiple Technologies Enable Complete CDC Sign Off from RTL
Meridian CDC’s fast performance, high precision, and high capacity enables quick clock domain crossing verification, from individual blocks to billion-gate SoC designs. Additionally, it is the simplest-to-use CDC solution in the industry, with integrated debug. Finally, its hierarchical flow delivers tremendous productivity boost with flat CDC accuracy.
What Meridian CDC Users are Saying
Of all the clock domain crossing tools we’ve evaluated, Real Intent’s Meridian CDC has the least number of false CDC errors (if any at all). Its setup on the clock and reset environment is painless, as it identifies the clock and reset relationship automatically. Thus, it requires almost no setup effort from the designer.
Meridian is high performance and finishes CDC analysis in minutes. It greatly simplifies designer’s task in CDC verification.
– Peter Teng, Sr., Engineering Manager, Renesas
We have assessed Real Intent Meridian CDC and compared it to another commercial tool. [The competitor’s tool] reports a lot of false errors, and as a result, our engineers pass over the errors.
Meridian CDC has a superior user interface — even beginners can use it.
The number of false errors is also dramatically decreased, thanks to its setup error detection.
– Semiconductor Designer, DeepChip.com EDA tool report