Meridian CDC – Clock Domain Crossing
Clock Domain Crossing Sign-off Solution
Meridian CDC is the fastest, highest capacity and most precise CDC solution in the market. It performs comprehensive structural and functional analysis to ensure that signals crossing asynchronous clock domains in ASIC or FPGA devices are received reliably. Meridian CDC is the only solution that enables all aspects of CDC sign-off for giga-gate SOC designs.
CDC bugs are a confluence of bad implementation, clock timing, and analog-like behavior in digital logic. As shown in Figure 1, if the signal, crossing from one domain to another relatively asynchronous domain, arrives too close to the receiving clock edge, the captured value is nondeterministic and leads to signal metastability. These errors are near impossible to detect and diagnose via simulation or in the lab, and result in frequent failures in the field that are expensive to fix.
Comprehensive CDC Sign-off
Meridian CDC is the only integrated solution in the industry that combines automatic CDC-intent analysis and metastability-aware formal analysis. Meridian CDC’s superior technology allows designers to use all of these strategies to guarantee complete CDC correctness. Its flexible top-down and bottom-up hierarchical analysis fits very well into the variety of methodologies used by design teams.
Meridian CDC supports Verilog, VHDL, and System Verilog languages. Meridian CDC automatically infers clock domain crossing intent from the design, and comprehensively analyzes clock/reset issues, incorrect or missing synchronization, glitch potential, reconvergence, structurally unsafe crossings, and potential data/control crossings that need functional verification.
If the signal crossing from one asynchronous domain to another arrives too close to the receiving clock edge, the captured value is nondeterministic.
Hierarchical CDC Methodology
The Hierarchical-CDC capability allows users to perform CDC verification on billion-gate SOCs within a matter of hours. The flow is founded on a unique Transparent Hierarchical Model derived from the block-level CDC analyses, and to be used at the chip level. The model is accurate enough to enable seamless hierarchical debug that is equivalent to a flat run. At the same time, the model is abstract enough that the flow generates unprecedented productivity gains that amount to an order of magnitude improvement in performance, capacity, and noise when applied to large SoC designs.
Smart Reporting and Powerful GUI
Meridian CDC’s smart reporting and efficient organization of design-data and tool findings keeps users focused on important issues despite massive SOC complexity. Helpful guidance and suggested actions help users pinpoint the source of problems quickly. Real Intent’s state-of-the-art design-intent debugger and analysis manager – iDebug – provides for user configurability and programmability with its command line interface (CLI).
Meridian CDC supports an integrated visualization tool. Pruned schematic views focus precisely on fault-related logic, and users are directed to related problematic RTL-source code within a few mouse clicks. This debug approach allows for easy investigation deep into complex designs to isolate the root cause for any reported warning or error.
Real Intent iDebug customized reporting for clock domain crossing warning
Simportal is a unique capability in Meridian CDC that generates dynamic CDC-verification models that can be compiled into a user’s simulation environment to further fortify CDC sign-off. It provides the most comprehensive and accurate CDC sign-off during dynamic verification.
Meridian CDC’s dynamic CDC verification models include metastability injection as well as functional checks.
The metastability injection models help uncover parts of the design that are not robustly protected against metastability effects. The functional check models help improve coverage on CDC signals, and uncover protocol inconsistencies and functional defects. If a monitor is triggered during simulation by a CDC functional-check violation, an error message is reported in the simulation log file.
Meridian CDC Features
- Automatic design environment captured from the design or SDC constraints
- Comprehensive clock-intent inference and analysis catches clock and reset issues
- Metastability aware formal analysis verifies control and data stability
- Flexible top-down and bottom-up hierarchical analysis to accommodate different design methodologies
- Transparent hierarchical model allows seamless debug equivalent to a flat run
Meridian CDC Benefits
- Highest capacity to enable CDC verification on billion-gate SoC designs
- Fastest performance for quick verification turnaround
- Most precise CDC reporting using integrated analysis
- Easiest-to-use CDC solution in the industry, and is template free
- Multiple technologies to enable complete CDC sign-off from RTL
- Hierarchical flow delivers a tremendous productivity boost