Meridian CDC – Clock Domain Crossing

Clock Domain Crossing Sign-off

Meridian CDC is the fastest, highest capacity and most precise clock domain crossing tool in the market for CDC sign-off. It performs comprehensive structural and functional analysis to ensure that signals crossing asynchronous clock domains in ASIC or FPGA devices are received reliably.

Designs now commonly have tens to hundreds of asynchronous clock domains. As a result,  clock domain crossing tools are a critical aspect of verification sign-off methodology.

Meridian CDC enables all aspects of CDC sign-off, including identifying issues related to metastability, loss of correlation, and glitch propagation.

Real Intent also offers Verix Multimode CDC, which provides the benefits of Meridian CDC and can cover all possible clocking scenarios in a single run.

Clock Domain Crossing - Meridian CDC

CDC Metastability

CDC bugs result from a combination of poor implementation, clock timing, and analog-like behavior in digital logic. For example, if a signal crossing from one domain to another relatively asynchronous domain arrives too close to the receiving clock edge, the captured value is nondeterministic and leads to signal metastability.

The resulting errors are nearly impossible to detect and diagnose via simulation or in the lab, and cause frequent failures in the field that are expensive to fix.

High Precision, Low Noise Results

Meridian CDC is the most precise solution in the market for clock domain crossing sign off.

Its proprietary static algorithms accurately interpret and deeply analyze clock domain crossing design structures.  The tool then categorizes the CDC paths into safe and unsafe paths.

This results in high precision, low noise results — even for the most complex CDC designs.

Unsafe

Safe

Clock domain crossing - Safe

Loss of Data

Loss of Correlation

Comprehensive CDC Sign-off

Clock domain crossings can also introduce other catastrophic failures in the design. For example, they can cause loss of correlation and glitch propagation problems.

Meridian CDC comprehensively analyses clock/reset structures and identifies all possible clock domain crossing issues. These include incorrect or missing synchronization, glitch potential, reconvergence, structurally unsafe crossings, and potential data/control crossings that need functional verification.

Meridian CDC supports Verilog, VHDL, and System Verilog languages and standard SDC or TCL formats for design constraints.

Smart Reporting and Powerful GUI

Meridian CDC’s smart reporting and organization enables users to efficiently focus on their designs most critical issues, regardless of the SOC complexity.

The tool provides helpful guidance, suggesting actions to help users to quickly pinpoint the problems sources. Real Intent’s design-intent debugger and analysis manager iDebug allows user configurability and programmability with its command line interface.

Meridian CDC also includes an integrated visualization tool; it has pruned schematic views that focus precisely on fault-related logic. It then directs users to related problematic RTL-source code within a few mouse clicks. This debug approach allows for easy investigation deep into complex designs to isolate the root cause for any reported warning or error.

Clock Domain Crossing Tool

Real Intent iDebug customized reporting for clock domain crossing warning

Hierarchical CDC verification

Hierarchical CDC reduces the # of violations found at the chip level

Hierarchical CDC Methodology

Meridian CDC’s hierarchical capability allows users to perform clock domain crossing verification on billion-gate SOCs within a matter of hours.

The hierarchical flow is founded on a unique transparent hierarchical model derived from block-level CDC analyses, and can be used at the chip level. This unique model provides unprecedented productivity g