Over the past decade, the move to System-on-Chip (SoC) design has dramatically increased chip sizes. An SOC can have many subcomponents with complex interactions and can stress capacity of verification flows. There can be a proliferation of complex reset interactions. Ensuring that a complex SoC works according to specification requires design and verification teams to spend an increasing amount of time on verification of these resets and their interaction.
This whitepaper starts with a discussion of hierarchical methodology to verify Reset Domain Crossings. It then elaborates on some of the requirements for such a methodology.