Meridian DFT – Multimode Design for Testability

Meridian DFT is a high capacity, multimode DFT static sign-off tool, which runs a comprehensive set of DFT rules to rapidly identify RTL and gate-level design violations to help designers improve scan testability and coverage.

Meridian DFT can be used for continuous DFT sign-off through completion of place & route:

1. During RTL design — to fix asynchronous set/reset, clock and connectivity issues early
2. After scan synthesis — to check for scan chain rule compliance
3. Following place & route – to assess & correct issues with scan chain reordering or netlist modification

Some of Meridian DFT’s unique characteristics enable designers to prepare their RTL and gate-level designs for the highest possible quality ATPG pattern generation and silicon success.

1. Multimode DFT, to check multiple sets of rules in a single run, reducing setup time, speeding up runtime, and accelerating debug
2. High capacity, to handle multimillion-gate designs in minutes with a low peak memory footprint
3. Comprehensive, fine-grained rules, to ensure high coverage at all design stages and help accelerate debug and root cause analysis
4. Low noise, minimize false positives and error duplication
5. Fast setup, which takes only hours instead of the weeks required with other DFT static tools
6. Fits easily with existing flows and DFT/ATPG tools

1. Multiple ATPG partitions. Meridian DFT saves substantial time by verifying multiple ATPG partitions in each run, eliminating the time-consuming process of running DFT static sign-off for each partition, with each partition requiring its own test mode.

2. Multiple constraint-sets. Meridian DFT verifies design for testability sign-off rules for multiple sets of design constraints in one run. Each constraint set corresponds to the types of ATPG patterns — such as uncompressed, compressed, diagnostic, connectivity.

3. Multiple constraint-sets across multiple test modes. The combination of the first two capabilities gives designers the flexibility to verify multiple constraint-sets across multiple test modes, in a single run.

Hierarchical Violation Categorization

Meridian DFT’s violation reporting lets you hierarchically categorize the violations by:

1. Rule — Specific violation types to check
2. Tiered Rule Group — Rule violation instances grouped & categorized by rule category, severity level, & test mode.
3. Policy/Violation Status — Container with multiple rule groups

Groups of related violations are shown in single report item. The group violations can then be toggled to expand or collapse.

If a root cause is identified, the violations associated with that root cause are grouped together. For example:

• Violations associated with a gated test clock reaching a flop are grouped by the clock gating instance.
• Violations associated with reset glitches are grouped by the convergence instance of the glitch sources.

Meridian DFT provides precise, actionable reporting of violations, through multiple mechanisms, including:

• Labeling schematics with rule-specific debug information, such as labeling the glitch sources and the convergence instances in the schematic for reset glitch rule
• For path-based rule violations, listing the complete debug path from one end to the other
• Annotating test mode attributes on nets
• Creating customized report policies and filtering rule violations for additional precision

Meridian DFT provides precise user instructions and guidance on set up changes required to fix specific violations. For example, it identifies and recommends the source of the clock root to be specified as a test clock.