Meridian RDC – Reset Domain Crossing

Case Study: SK Hynix — Advanced Reset Design Crossing Methodology
New: User Evaluation Criteria & Results for Meridian RDC

Reset Domain Crossing Sign-off

Meridian RDC is the industry’s fastest, lowest noise, multi-scenario reset domain crossing sign-off tool. It performs both structural and functional analysis to ensure that signals crossing reset domains behave reliably.

Meridian RDC identifies reset functionality problems due to

  • Metastability, e.g. arising from software and/or low power resets
  • Glitches on asynchronous resets
  • Reconvergence of synchronized resets

Meridian RDC is the only solution in the industry that enables comprehensive, multi-scenario reset domain crossing sign-off —  it requires only one set up, runs multiple reset scenarios in one run — in parallel for maximum speed, produces one consolidated, low-noise violation report.

This minimizes engineering effort and debug time — dramatically improving usability in the design flow.

Reset Domain Crossing

What is Reset Domain Crossing?

Reset domain crossing (RDC) refers to a path in the design where the source & destination elements (flops, latches, clock gates) operate on different independent resets. Reset domain crossing sign-off tools & methodologies ensure the signals crossing the reset domains function reliably.

What is Metastability?

Metastability occurs when an asynchronous reset from one reset domain causes a transition too close to the clock edge of a flip-flop in another reset domain or without a reset, causing a non-deterministic flip-flop value that propagates throughout the design resulting in functional failures.

Reset Domain Crossing

Reset Domain Crossing untimed path

Untimed path through the reset port

Reset Domain Crossing Chip-killer Bugs

Poor reset architecture and/or design can result in unreliable functional resets, causing intermittent catastrophic chip failures.

Metastability may result at a reset domain crossing when an asynchronous reset is asserted/deasserted. Glitches may cause spurious resets when an asynchronous reset is generated by combinatorial logic. Functional loss of correlation of synchronized resets may result from reconvergence.

As shown in the figure, static timing analysis (STA) constrains normal timing paths (shown in blue). But, if SOFT_RST-A asserts, while SOFT_RST-B does not assert, an untimed path is created through the reset port (shown in red). This may result in intermittent unpredictable silicon behavior.

These chip-killer errors are not caught in static solutions like STA, clock domain crossing (CDC) tools, or through simulation. They result in chip failures in the field that are difficult to diagnose and expensive to fix.

Precision Reset Domain Crossing Sign-off

Meridian RDC automatically extracts resets and reset domains and performs precise RDC analysis. Meridian RDC’s unique technology allows designers to use effective strategies to guarantee complete reset domain crossing correctness. It verifies:

  • Asynchronous resets that are crossing reset domains will not cause metastability when resets are activated or de-activated
  • Reconverging synchronized resets are functionally correlated
  • Asynchronous resets are glitch-free

This provides best-in-class quality of results for reset integrity in the market.

Reset Groups & Scenarios

Meridian RDC allows you to define several related reset signals.  You can specify the reset relationships using simple reset groups or through advanced reset scenarios.

For more precise modeling of the reset relationships, you can also include constraints that impact reset behavior. Additionally, our unique reset scenario specification capability allows you to model the reset behavior for multiple transitions and edge accurate granularity.

The dependencies between multiple resets can be defined in both time-based and event-based manners. By automatically generating signal waveforms from reset specifications, Meridian RDC visualizes  correct reset relationships.

This powerful combination of unique functional analysis and reset behavior abstraction significantly reduces noise when reporting reset domain crossing violations.

Hierarchical RDC Flow with Flat RDC Accuracy

Meridian RDC’s advanced hierarchical flow helps design teams effectively manage reset domain crossing sign off even for extremely large designs, providing unprecedented productivity gains. The high level partitioning significantly improves runtime by dramatically reducing the volume of data to be analyzed; RDC analysis can be performed on billion gate SoCs in a matter of hours.

Additionally, late RTL changes that can affect entire chip are contained to enable successful RDC Sign off.

Meridian RDC utilizes a unique transparent hierarchical model at the chip level, derived from block level RDC analysis. Each IP or block can be independently verified and then assembled at a higher level. Meridian RDC’s hierarchical database model saves fully accurate design information, in contrast to black boxes with only abstracted information at the ports.

The result is seamless debug that is equivalent in accuracy to a flat run – for fully confident reset domain crossing sign off.

RDC Analysis Parallelization Accelerates Performance

Meridian RDC utilizes parallelism to accelerate performance for both flat and hierarchical reset domain crossing runs. This unique parallelization of RDC verification flow provides order of magnitude improvement in run time and debugging effectiveness.

The parallel runs can be on multiple cores on the same server or distributed across a server farm.

Smart Reporting and Powerful GUI

Meridian RDC’s smart reporting keeps users focused on important issues through efficient organization of findings. Helpful guidance and suggested actions help users pinpoint the source of the problems quickly. Real Intent’s state-of-the-art design intent debugger and analysis manager—iDebug—provides for user configurability and programmab