Reset Domain Crossing – Meridian RDC2018-12-28T22:36:14+00:00

Meridian RDC – Reset Domain Crossing

White Paper: Making Sure Resets Don’t Kill Your SoCs

Reset Domain Crossing Sign-off Solution

Meridian RDC is the fastest and most precise reset domain crossing sign-off tool on the market. It performs comprehensive static analysis to ensure that signals crossing reset domains function reliably. Among other things, Meridian RDC identifies metastability problems arising from software and/or low power resets.

Reset functionality may be incorrect due to metastability, glitches on asynchronous resets, or reconvergence of synchronized resets. Metastability may result at a reset domain crossing when an asynchronous reset is asserted/deasserted. Glitches may cause spurious resets when an asynchronous reset is generated by combinatorial logic. Functional loss of correlation of synchronized resets may result from reconvergence.

Meridian RDC is the only solution that enables comprehensive reset domain crossing sign-off.

Untimed path through the reset port

RDC Chip-killer Bugs

Poor reset architecture and/or design can result in unreliable functional resets, causing intermittent catastrophic chip failures. As shown in the figure, static timing analysis (STA) constrains normal timing paths (shown in blue). But, if SOFT_RST-A asserts, while SOFT_RST-B does not assert, an untimed path is created through the reset port (shown in red). This may result in intermittent unpredictable silicon behavior.

These chip-killer errors are not caught in static solutions like STA, clock domain crossing (CDC) tools, or through simulation. They result in chip failures in the field that are difficult to diagnose and expensive to fix.

Precise RDC Sign-off

Meridian RDC is the only solution in the industry that automatically extracts resets and reset domains and performs precise RDC analysis. Meridian RDC’s unique technology allows designers to use effective strategies to guarantee complete RDC correctness. It verifies:

  • Asynchronous resets that are crossing reset domains will not cause metastability when resets are activated or de-activated
  • Reconverging synchronized resets are functionally correlated
  • Asynchronous resets are glitch-free

This provides best-in-class quality of results for reset integrity in the market.

Hierarchical RDC Methodology

Hierarchical RDC capability allows users to perform RDC verification on billion-gate SoCs within a matter of hours. The flow uses a unique Transparent Hierarchical Model (THM), from the block level RDC analysis, to be used at the chip level. This allows seamless debug that is equivalent to a flat run. The flow provides unprecedented productivity gains that are an order of magnitude improvement in performance, capacity, and noise when applied to large SoC designs.

Smart Reporting and Powerful GUI

Meridian RDC’s smart reporting keeps users focused on important issues through efficient organization of findings. Helpful guidance and suggested actions help users pinpoint the source of the problems quickly. Real Intent’s state-of-the-art design intent debugger and analysis manager—iDebug—provides for user configurability and programmability with its command line interface (CLI). All the RDC analysis data is stored in a database that can be accessed through the CLI. Users can customize the debug methodology to match their design flows using spreadsheet reports, graphical reports, scripting, and so on.

Meridian RDC supports an integrated visualization tool. Pruned schematic views focus on fault-related logic, and with a few mouse clicks, users are directed to the RTL source code that caused the problem. This debug approach allows for easy investigation deep into the design to isolate the root cause for any warnings and errors.

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  • Automatic design environment capture from designs or SDC constraints
  • Comprehensive clock and reset inference with automated setup checks ensure the integrity of results
  • Detection and reporting of safe crossings
  • Low noise metastability checking on unsafe crossings when resets are activated and de-activated
  • High performance and capacity for block, IP, and and full-chip levels
  • Ensures asynchronous resets are glitch-free
  • Ensures functional correlation of synchronized resets
  • Annotated schematics, waveforms, and the source browsing using iVision
  • Debug flow and status tracking is facilitated with iDebug GUI and CLI


  • Sign-off of resets w.r.t. metastability issues, glitch issues, and functional correlation of synchronized resets ensures predictable chip functionality
  • Leverages proven CDC engines and flow for reliable results and easy adoption
  • Enables RDC verification on giga-gate SoC designs
  • Fast performance for quick verification turnaround
  • Precise non-overlapping RDC reporting using integrated analysis minimizes the debug cycle.
  • Fast run times, accuracy, and ease of use make the Meridian RDC solution the best in the industry for comprehensive reset sign-off