Poor reset architecture and/or design can result in unreliable functional resets, causing intermittent catastrophic chip failures.
Metastability may result at a reset domain crossing when an asynchronous reset is asserted/deasserted. Glitches may cause spurious resets when an asynchronous reset is generated by combinatorial logic. Functional loss of correlation of synchronized resets may result from reconvergence.
As shown in the figure, static timing analysis (STA) constrains normal timing paths (shown in blue). But, if SOFT_RST-A asserts, while SOFT_RST-B does not assert, an untimed path is created through the reset port (shown in red). This may result in intermittent unpredictable silicon behavior.
These chip-killer errors are not caught in static solutions like STA, clock domain crossing (CDC) tools, or through simulation. They result in chip failures in the field that are difficult to diagnose and expensive to fix.