Reset Domain Crossing – Meridian RDC2019-02-22T19:23:33+00:00

Meridian RDC – Reset Domain Crossing

White Paper: Making Sure Resets Don’t Kill Your SoCs

Reset Domain Crossing Sign-off Solution

Meridian RDC is the fastest and most precise reset domain crossing sign-off tool on the market. It performs comprehensive static analysis to ensure that signals crossing reset domains function reliably. Among other things, Meridian RDC identifies metastability problems arising from software and/or low power resets.

Reset functionality may be incorrect due to metastability, glitches on asynchronous resets, or reconvergence of synchronized resets. Metastability may result at a reset domain crossing when an asynchronous reset is asserted/deasserted. Glitches may cause spurious resets when an asynchronous reset is generated by combinatorial logic. Functional loss of correlation of synchronized resets may result from reconvergence.

Meridian RDC is the only solution that enables comprehensive reset domain crossing sign-off.

Untimed path through the reset port

RDC Chip-killer Bugs

Poor reset architecture and/or design can result in unreliable functional resets, causing intermittent catastrophic chip failures. As shown in the figure, static timing analysis (STA) constrains normal timing paths (shown in blue). But, if SOFT_RST-A asserts, while SOFT_RST-B does not assert, an untimed path is created through the reset port (shown in red). This may result in intermittent unpredictable silicon behavior.

These chip-killer errors are not caught in static solutions like STA, clock domain crossing (CDC) tools, or through simulation. They result in chip failures in the field that are difficult to diagnose and expensive to fix.

Precision RDC Sign-off

Meridian RDC automatically extracts resets and reset domains and performs precise RDC analysis. Meridian RDC’s unique technology allows designers to use effective strategies to guarantee complete RDC correctness. It verifies:

  • Asynchronous resets that are crossing reset domains will not cause metastability when resets are activated or de-activated
  • Reconverging synchronized resets are functionally correlated
  • Asynchronous resets are glitch-free

This provides best-in-class quality of results for reset integrity in the market.

Reset Groups & Scenarios

Meridian RDC allows you to define several related reset signals.  You can specify the reset relationships using simple reset groups or through advanced reset scenarios.

For more precise modeling of the reset relationships, you can also include constraints that impact reset behavior. Additionally, our unique reset scenario specification capability allows you to model the reset behavior for multiple transitions and edge accurate granularity.

The dependencies between multiple resets can be defined in both time-based and event-based manners. By automatically generating signal waveforms from reset specifications, Meridian RDC visualizes  correct reset relationships.

This powerful combination of unique functional analysis and reset behavior abstraction significantly reduces noise when reporting violations.

Hierarchical RDC Flow with Flat RDC Accuracy

Meridian RDC’s advanced hierarchical flow helps design teams effectively manage reset domain crossing sign off even for extremely large designs, providing unprecedented productivity gains. The high level partitioning significantly improves runtime by dramatically reducing the volume of data to be analyzed; RDC analysis can be performed on billion gate SoCs in a matter of hours.

Additionally, late RTL changes that can affect entire chip are contained to enable successful RDC Sign off.

Meridian RDC utilizes a unique transparent hierarchical model at the chip level, derived from block level RDC analysis. Each IP or block can be independently verified and then assembled at a higher level. Meridian RDC’s hierarchical database model saves fully accurate design information, in contrast to black boxes with only abstracted information at the ports.

The result is seamless debug that is equivalent in accuracy to a flat run – for fully confident reset domain crossing sign off.

RDC Analysis Parallelization Accelerates Performance

Meridian RDC utilizes parallelism to accelerate performance for both flat and hierarchical reset domain crossing runs. This unique parallelization of RDC verification flow provides order of magnitude improvement in run time and debugging effectiveness.

The parallel runs can be on multiple cores on the same server or distributed across a server farm.

Smart Reporting and Powerful GUI

Meridian RDC’s smart reporting keeps users focused on important issues through efficient organization of findings. Helpful guidance and suggested actions help users pinpoint the source of the problems quickly. Real Intent’s state-of-the-art design intent debugger and analysis manager—iDebug—provides for user configurability and programmability with its command line interface (CLI). All the RDC analysis data is stored in a database that can be accessed through the CLI. Users can customize the debug methodology to match their design flows using spreadsheet reports, graphical reports, scripting, and so on.

Meridian RDC supports an integrated visualization tool. Pruned schematic views focus on fault-related logic, and with a few mouse clicks, users are directed to the RTL source code that caused the problem. This debug approach allows for easy investigation deep into the design to isolate the root cause for any warnings and errors.

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Features

  • Automatic design environment capture from designs or SDC constraints
  • Comprehensive clock and reset inference with automated setup checks ensure the integrity of results
  • Detection and reporting of safe crossings
  • Low noise metastability checking on unsafe crossings when resets are activated and de-activated
  • High performance and capacity for block, IP, and and full-chip levels
  • Ensures asynchronous resets are glitch-free
  • Ensures functional correlation of synchronized resets
  • Annotated schematics, waveforms, and the source browsing using iVision
  • Debug flow and status tracking is facilitated with iDebug GUI and CLI

Benefits

  • Sign-off of resets w.r.t. metastability issues, glitch issues, and functional correlation of synchronized resets ensures predictable chip functionality
  • Leverages proven CDC engines and flow for reliable results and easy adoption
  • Enables RDC verification on giga-gate SoC designs
  • Fast performance for quick verification turnaround
  • Precise non-overlapping RDC reporting using integrated analysis minimizes the debug cycle.
  • Fast run times, accuracy, and ease of use make the Meridian RDC solution the best in the industry for comprehensive reset sign-off