Prakash Narain, Ph.D.
President, CEO

Dr. Prakash Narain’s career spans IBM, AMD and Sun where he got hands on experience with all aspects of IC design, CAD tools design and methodology. He was the project leader for test and verification for UltraSPARC III at Sun Microsystems. He was an architect of the Mercury Design System at AMD. He has architected and developed CAD tools for test and verification for IBM EDA. Dr. Narain has a Ph.D. from the University of Illinois at Champaign-Urbana where his thesis focus was on algorithms for high level testing and verification.

Rajiv Kumar
VP, Engineering

Rajiv Kumar spent almost 12 years at Hewlett-Packard in both engineering and managerial capacities, where he worked on several generations of the PA-RISC processor and HP’s high-end server systems, along with the joint development of Itanium processor with Intel’s engineering team. He was a key architect for HP’s transition from 32-bit to 64-bit platform where he led over 100 engineers in delivering HP’s first 64-bit system. Mr. Kumar holds graduate degrees in management from Stanford and in computer science from University of Oregon.

Oren Katzir
VP, App Eng & Bus Dev

Oren leads Real Intent’s Application Engineering (AE) team that supports the sales team and customers. He brings to his new position more than 15 years of experience in engineering management, SoC and ASIC design, and development of SoC design tool flows. Previously, Oren was an engineering manager at Intel, leading an SoC engineering team.  He also held engineering management positions at Sagantec, Silicon Design Systems, Transchip and Silicon Value. Oren holds a BS in computer engineering from Technion-Israel Institute of Technology.

Pranav Ashar, Ph.D.
Chief Technology Officer

Dr. Pranav Ashar brings more than two decades of EDA expertise to Real Intent. Previously, he was Department Head at NEC Labs in Princeton, NJ where he developed a number of influential EDA technologies. He has authored about 70 refereed publications with more than 1500 citations, and co-authored the book “Sequential Logic Synthesis”. His paper titled “Accelerating Boolean Satisfiability with Configurable Hardware” was selected as one of 25 significant contributions from 20 Years at an IEEE Symposium. He has 35 patents granted or pending. Pranav was adjunct CSEE faculty at Columbia University where he  taught VLSI design and verification courses. Dr. Ashar received his Ph.D. in EECS from the University of California, Berkeley.

Vishnu Vimjam, Ph.D.
Chief Architect

Dr. Vishnu Vimjam has more than a decade of experience in developing state-of-the-art EDA verification tools. As chief architect, Vishnu applies his deep technical knowledge, close attention to detail and expert knowledge of customers’ challenging verification needs to architect Real Intent’s world-class solutions for accelerating RTL sign-off. He began his career as a formal verification R&D engineer at Real Intent 11 years ago, following consecutive summer internships at Intel, and quickly became engineering manager. He holds an engineering degree from Jawaharlal Nehru Technological University, and M.S. and Ph.D. degrees in computer engineering from Virginia Polytechnic Institute and State University.