Western Digital worked towards enhancing their CDC methodology to handle the various clock and reset scenarios.
To do so, they created architecture-specific assumptions and constraints, such as:
“For example clock through clk_blk_a is off when reset through rst_blk_a is asserted”.
Western Digital partnered with Real Intent to enhance Real Intent’s Meridian CDC tool to understand these architectural assumptions. Independently, they worked on formal and dynamic means to verify the above assumptions and constraints.
This enhanced methodology allowed them to identify whether there were any incorrect reset synchronization issues.
By reducing the noise significantly in the CDC analysis, they could focus on actual violations. It also allowed them to catch reset & clock connectivity issues when the IP didn’t connect to the correct signals from the central unit.
They signed-off on using this methodology the first time. The design was
- ~6 million gates
- Had ~64 blocks with different resets
Without the enhanced methodology, Western Digital used to get around 800K reset related CDC violations on this SoC. With the enhanced methodology:
- They had zero violations
- Missed none of the issues
Western Digital also used netlist simulations to confirm there were no real reset related CDC violations on the design.