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Accelerating design sign-off: Comprehensive CDC verification and RTL analysis with performance and capacity no other company can match, and low-noise reporting. Quick and easy debug eliminates complex failure modes of SoCs.

News

September 30, 2014 – Real Intent Delivers Next Generation of Meridian CDC for Clock Domain Crossing Sign-off of SoC Designs More

September 30, 2014 – The evolution of lint More


October 8, 2014 – Real Intent to Exhibit at First DVCon Europe More

October 2, 2014 – DeepChip: Graham Bell’s Synopsys-Verdi Interop Trip Report More


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Newsletter
September 2014, Real Verification News More

May 2014, Real Verification News More

February 2014, Real Verification News More

Upcoming Events
Design Solution Forum, Japan More
ARM TechCon Santa Clara, CA More
DVClub Shanghai, China More

DAC 2014 San Francisco, CA More

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Articles
Real Intent Blog
October 2014 – DeepChip: Graham Bell’s Synopsys-Verdi Interop Trip Report More

September 30, 2014 – The evolution of lint More

July 2014 – It’s time to embrace objective-driven verification More

June 2014 – Experts At The Table: Where Do We Stand With CDC? Part 1 Part 2  Part 3

Fundamentals of Clock Domain Crossing Verification: Part Three More

Fundamentals of Clock Domain Crossing Verification: Part Two More

Fundamentals of Clock Domain Crossing Verification: Part One More

Static Verification Leads to New Age of SoC Design More

Press Releases
October 08, 2014 – Real Intent to Exhibit at First DVCon Europe More

September 30, 2014 – Real Intent Delivers Next Generation of Meridian CDC for Clock Domain Crossing Sign-off of SoC Designs More

September 26, 2014 – Real Intent to Exhibit at Design Solution Forum 2014 in Japan More

September 24, 2014 – Real Intent Showcases RTL Sign-off Solutions at ARM TechCon 2014 More

White Papers
CDC Methodology for Fast-to-slow Clocks. View

Clock and Reset Ubiquity: A CDC Verification Perspective. View

Clock Domain Crossing Demystified: The Second Generation Solution for CDC Verification. View

Webinars
Automatic RTL Verification with Ascent IIV: Find Bugs Before Simulation. View