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Accelerating design sign-off: Comprehensive CDC verification and RTL analysis with performance and capacity no other company can match, and low-noise reporting. Quick and easy debug eliminates complex failure modes of SoCs.

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October 2017– DeepChip: One user’s eval of Real Intent AutoFormal and Ascent Lint More

October 2017– DeepChip: Cliff Cummings on Real Intent More


December 2017– DeepChip: Prakash and Anirudh spar on Real Intent vs Cadence Linting More

November 2017 – Real Intent to Exhibit at SemIsrael Expo 2017 More


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Real Intent Blog
December 2017– DeepChip: Prakash and Anirudh spar on Real Intent vs Cadence Linting More

October 2017– DeepChip: One user’s eval of Real Intent AutoFormal and Ascent Lint More

October 2017– DeepChip: Cliff Cummings on Real Intent More

September 2017– DeepChip: Prakash sees 3X revenue in 2017 More

Real Intent on DeepChip’s Cheesy List for DAC 2017 More

Join Real Intent at DAC as we Unveil our Revolutionary Multimode Sign-off Solution! More

Fix X-pessimism in Netlists with Practical Techniques More

The Switch from Atrenta to Real Intent for CDC, Lint, and X-prop More
Press Releases
November 15, 2017 – Real Intent to Exhibit at SemIsrael Expo 2017 More

October 26, 2017 – Real Intent to Exhibit at ARM Tech Symposia in Taiwan More

June 16, 2017– Real Intent to Exhibit New Verix Product at DAC in Austin More

June 15, 2017– Real Intent’s New Verix Product Family Delivers First Intent-Driven Multimode RTL Sign-off of SoC Designs More

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Bulletproofing FSM Verification View

True Multimode CDC Sign-off View

The Next Step in High-Reliability FPGA Signoff View

Billion Gate CDC Sign-off Done Right View

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Solving the Reset Design Challenges of Today’s SoCs View