Home

Reply
Accelerating design sign-off: Comprehensive CDC verification and RTL analysis with performance and capacity no other company can match, and low-noise reporting. Quick and easy debug eliminates complex failure modes of SoCs.

News

May 14, 2013 – Real Intent and DeFacTo Deliver Combined RTL Sign-off Flow for Clock Domain Crossing and Design for Test More

May 9, 2013 – DeepChip: Real Intent’s not-so-secret DVcon’13 Report More


May 23, 2013 – Real Intent to Exhibit Verification Solutions, Demonstrate New RTL Flows, and Present at the Design Automation Conference 2013 More

May 21, 2013 – Real Intent Achieves More Than 70-Percent Revenue Growth in First Half of 2013 More

Video

Real Intent is on Gary Smith’s “What to see at DAC 2013” List! More
Newsletter
May 2013, Real Verification News More

February 2013, Real Verification News More

Upcoming Events
DAC 2013, Austin, TX More

Twitter LinkedIn Youtube RSS Feed
Articles
Real Intent Blog
May 2013 – “DeepChip: Real Intent’s not-so-secret DVcon’13 Report” More

March 2013 – “Experts At The Table: Verification Strategies” Part 1 Part 2 Part 3

March 2013 – “Clock-domain and reset verification in the low-power design era” More

January 2013 – “Clock Domain Crossing Demystified” More

Real Intent is on Gary Smith’s “What to see at DAC” List! More

Your Real Intent Invitation to Fun and Fast Verification at DAC More

DeepChip: “Real Intent’s not-so-secret DVcon’13 Report” More

TechDesignForum: Better analysis helps improve design quality More
Press Releases
Real Intent to Exhibit Verification Solutions, Demonstrate New RTL Flows, and Present at the Design Automation Conference 2013 More

Real Intent Achieves More Than 70-Percent Revenue Growth in First Half of 2013 More

Real Intent and DeFacTo Deliver Combined RTL Sign-off Flow for Clock Domain Crossing and Design for Test More

White Papers
Clock and Reset Ubiquity: A CDC Verification Perspective. View

Clock Domain Crossing Demystified: The Second Generation Solution for CDC Verification. View

Webinars
Automatic RTL Verification with Ascent IIV: Find Bugs Before Simulation. View