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Accelerating design sign-off: Comprehensive CDC verification and RTL analysis with performance and capacity no other company can match, and low-noise reporting. Quick and easy debug eliminates complex failure modes of SoCs.

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March 29 2016 – Real Intent at CDNLive Silicon Valley 2016 Exhibits Its Ascent and Meridian Solutions More

March 28 2016 – Real Intent to Present Technical Seminar in Israel on Its RTL Sign-off and SoC Verification More


May 2 2016– Real Intent to Exhibit at CDNLive EMEA 2016 in Munich More

April 1 2016 – SiliconIndia names Real Intent in its 2016 list of 20 Most Promising Semiconductor Companies More


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DVCon Europe,November 11-12, 2015 More

SemIsrael Expo 2015,November 17, 2015 More

DVCon 2016,February 29 – March 3, 2016 More

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Articles
Real Intent Blog
April 2016 – SiliconIndia names Real Intent in its 2016 list of 20 Most Promising Semiconductor Companies More

December 2015 – DeepChip.com Survey: “Real Intent to possibly replace SpyGlass? More

December 2015 – X-Pessimism: A Realistic Approach is Needed More

October 2015 – Real Intent DAC’15 survey on CDC bugs, X propagation, constraints More

DeepChip.com Survey: “Real Intent to possibly replace SpyGlass?” More

Best of “Real Talk”, Q4 Summary and Latest Videos More

Exposing and Eliminating X-optimism Bugs in RTL More

Is SystemVerilog the COBOL of Electronic Design? More
Press Releases
May 2, 2016 – Real Intent to Exhibit at CDNLive EMEA 2016 in Munich More

March 29, 2016 –Real Intent at CDNLive Silicon Valley 2016 Exhibits Its Ascent and Meridian Solutions More

March 28, 2016 –Real Intent to Present Technical Seminar in Israel on Its RTL Sign-off and SoC Verification More

White Papers
CDC Methodology for Fast-to-slow Clocks. View

Clock and Reset Ubiquity: A CDC Verification Perspective. View

Clock Domain Crossing Demystified: The Second Generation Solution for CDC Verification. View

Webinars
Automatic RTL Verification with Ascent IIV: Find Bugs Before Simulation. View