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Accelerating design sign-off: Comprehensive CDC verification and RTL analysis with performance and capacity no other company can match, and low-noise reporting. Quick and easy debug eliminates complex failure modes of SoCs.

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May 28, 2015 – Real Intent Sets the Pace at DAC 2015 for Fun, Faster Verification and Design Success More

May 21, 2015 – Real Intent Delivers Major Innovation in Clock Domain Crossing Sign-off of SoC Designs More


July 24 2015 – Making a Difference Still Does Make a Difference More

May 31, 2015 – Technology trends demand netlist-level CDC verification More


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February 2015, Real Verification News More

September 2014, Real Verification News More

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Articles
Real Intent Blog
July 2015 – Making a Difference Still Does Make a Difference More

May 2015 – Technology trends demand netlist-level CDC verification More

March 2015 – VerifNews Interview with Graham Bell More

March 2015 – Shifting Mindsets: Static Verification Transforms SoC Design at RT Level More

Advanced FPGA Sign-off Includes DO-254 Missing DAC? More

#2 on GarySmithEDA What to See @ DAC List – Why? More

SoC Verification: There is a Stampede! More

Drilling Down on the Internet-of-Things (IoT) More
Press Releases
May 28, 2015 – Real Intent Sets the Pace at DAC 2015 for Fun, Faster Verification and Design Success More

May 21, 2015 – Real Intent Delivers Major Innovation in Clock Domain Crossing Sign-off of SoC Designs More

April 21, 2015 – Real Intent to Exhibit at CDNLive EMEA 2015 in Munich More

White Papers
CDC Methodology for Fast-to-slow Clocks. View

Clock and Reset Ubiquity: A CDC Verification Perspective. View

Clock Domain Crossing Demystified: The Second Generation Solution for CDC Verification. View

Webinars
Automatic RTL Verification with Ascent IIV: Find Bugs Before Simulation. View