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Accelerating design sign-off: Comprehensive CDC verification and RTL analysis with performance and capacity no other company can match, and low-noise reporting. Quick and easy debug eliminates complex failure modes of SoCs.

News

December 08 2015 – X-Pessimism: A Realistic Approach is Needed More

November 10 2015 – Real Intent to Present at SemIsrael Expo 2015 and Exhibit Its Verification and Advanced Sign-off Tools More


January 29 2016 – Real Intent Presents Free Webinar on Feb. 3, 2015: Ensuring Robust RTL Sign-off for Altera FPGAs More

December 18 2015 – DeepChip.com Survey: “Real Intent to possibly replace SpyGlass?” More


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Upcoming Webinar
Ensuring Robust RTL Sign-off for Stratix® FPGA and SoC Designs
Wednesday Feb 3,
10am Pacific Time
Newsletter
Sep 2015, Real Verification News More

May 2015, Real Verification News More

February 2015, Real Verification News More

Upcoming Events

DVCon Europe,November 11-12, 2015 More

SemIsrael Expo 2015,November 17, 2015 More

DVCon 2016,February 29 – March 3, 2016 More

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Articles
Real Intent Blog
December 2015 – DeepChip.com Survey: “Real Intent to possibly replace SpyGlass? More

December 2015 – X-Pessimism: A Realistic Approach is Needed More

October 2015 – Real Intent DAC’15 survey on CDC bugs, X propagation, constraints More

October 2015 – CEO Insight: Is Silicon the New Fabric for Our Lives? More

DeepChip.com Survey: “Real Intent to possibly replace SpyGlass?” More

Best of “Real Talk”, Q4 Summary and Latest Videos More

Exposing and Eliminating X-optimism Bugs in RTL More

Is SystemVerilog the COBOL of Electronic Design? More
Press Releases
January 29, 2016 – Real Intent Presents Free Webinar on Feb. 3, 2015: Ensuring Robust RTL Sign-off for Altera FPGAs More

November 10, 2015 – Real Intent to Present at SemIsrael Expo 2015 and Exhibit Its Verification and Advanced Sign-off Tools in Booth #38 More

November 04, 2015 – Real Intent to Exhibit Leading Verification Solutions at Second Annual DVCon Europe More

White Papers
CDC Methodology for Fast-to-slow Clocks. View

Clock and Reset Ubiquity: A CDC Verification Perspective. View

Clock Domain Crossing Demystified: The Second Generation Solution for CDC Verification. View

Webinars
Automatic RTL Verification with Ascent IIV: Find Bugs Before Simulation. View