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Accelerating design sign-off: Comprehensive CDC verification and RTL analysis with performance and capacity no other company can match, and low-noise reporting. Quick and easy debug eliminates complex failure modes of SoCs.

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January 23, 2017–Concept Engineering’s RTLVision Debugger and Viewer to Power Real Intent’s Verification Solutions More

December 16, 2016– DeepChip: Real Intent tied for #2 overall for Best EDA of 2016 More


February 23, 2017– DeepChip: Prakash on DVcon’16, portable stimulus, the end of simulation More

February 21, 2017–Real Intent to Exhibit at DVCon U.S. 2017 Next Week More


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Dec 2016, Real Verification News More

May 2016, Real Verification News More

Feb 2016, Real Verification News More

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DAC Austin TX, June 19 – 21 More

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Articles
Real Intent Blog
February 2017– DeepChip: Prakash on DVcon’16, portable stimulus, the end of simulation More

December 2016– DeepChip: Real Intent tied for #2 overall for Best EDA of 2016 More

August 2016–Peggy Aycinena: Real Intent: A sustained culture of Respect & Innovation More

May 2016– DeepChip: User on why he switched from Atrenta to RealIntent for lint/CDC/X More

DeepChip.com Survey: “Real Intent to possibly replace SpyGlass?” More

Best of “Real Talk”, Q4 Summary and Latest Videos More

Exposing and Eliminating X-optimism Bugs in RTL More

Is SystemVerilog the COBOL of Electronic Design? More
Press Releases
February 21, 2017–Real Intent to Exhibit at DVCon U.S. 2017 Next Week More

January 23, 2017– Concept Engineering’s RTLVision Debugger and Viewer to Power Real Intent’s Verification Solutions More

November 15, 2016– Real Intent Announces Meridian RDC, a New Product for Reset Domain Crossing Sign-off More

November 11, 2016– Real Intent to Exhibit at ARM Tech Symposia in Taiwan Next Week More

White Papers
The Next Step in High-Reliability FPGA Signoff View

Billion Gate CDC Sign-off Done Right View

Making Sure Resets Don’t Kill Your SoCs
View

Setting a New Lint Benchmark. View

Webinars
Automatic RTL Verification with Ascent IIV: Find Bugs Before Simulation. View