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Accelerating design sign-off: Comprehensive CDC verification and RTL analysis with performance and capacity no other company can match, and low-noise reporting. Quick and easy debug eliminates complex failure modes of SoCs.

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June 16, 2017– Real Intent to Exhibit New Verix Product at DAC in Austin More

June 15, 2017– Real Intent’s New Verix Product Family Delivers First Intent-Driven Multimode RTL Sign-off of SoC Designs More


September 2017– Peggy Aycinena: Real Intent: Leveraging on Investments More

August 2017– EE Journal: Clocks, Xs, and Resets: Real Intent Discusses New Solutions More


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Articles
Real Intent Blog
September 2017– Peggy Aycinena: Real Intent: Leveraging on Investments More

August 2017– EE Journal: Clocks, Xs, and Resets: Real Intent Discusses New Solutions More

February 2017– DeepChip: Prakash on DVcon’16, portable stimulus, the end of simulation More

December 2016– DeepChip: Real Intent tied for #2 overall for Best EDA of 2016 More

Real Intent on DeepChip’s Cheesy List for DAC 2017 More

Join Real Intent at DAC as we Unveil our Revolutionary Multimode Sign-off Solution! More

Fix X-pessimism in Netlists with Practical Techniques More

The Switch from Atrenta to Real Intent for CDC, Lint, and X-prop More
Press Releases
June 16, 2017– Real Intent to Exhibit New Verix Product at DAC in Austin More

June 15, 2017– Real Intent’s New Verix Product Family Delivers First Intent-Driven Multimode RTL Sign-off of SoC Designs More

January 23, 2017– Concept Engineering’s RTLVision Debugger and Viewer to Power Real Intent’s Verification Solutions More

November 15, 2016– Real Intent Announces Meridian RDC, a New Product for Reset Domain Crossing Sign-off More

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True Multimode CDC Sign-off View

The Next Step in High-Reliability FPGA Signoff View

Billion Gate CDC Sign-off Done Right View

Making Sure Resets Don’t Kill Your SoCs
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Solving the Reset Design Challenges of Today’s SoCs View