Verix SimFix – X-Pessimism Correction
X-Pessimism Correction in Gate-level Simulation
The Verix X-Pessimism correction system (SimFix) enables accurate gate-level simulations (GLS) that are necessary for a thorough verification sign-off. Inaccurate simulation is caused by the propagation of pessimistic unknowns (e.g. X’s) in netlist designs. SimFix uses mathematical methods to identify conditions under which pessimism can occur, and to determine the correct value when those conditions occur.
It then generates auxiliary SimPortal files that, when used in simulation, will detect and correct pessimism so that the simulation accurately models real hardware. Without SimFix, GLS verification is compromised by inaccurate random initialization or costly synthesis switches, neither of which is foolproof and often still requires long and laborious gate-level debug.
The Unknown is Dangerous
Language standards define an X as an “unknown” when simulation cannot definitely resolve a signal value. Due to simulation semantics, X’s can cause X-optimism in RTL simulations and X-pessimism in netlist simulations. X-optimism can result in missing functional bugs at RTL because the X’s may not be propagated. On the other hand, X-pessimism results in X’s that should not even be there, making it hard to get netlist simulations up and running because of the cascade effect when the X’s are propagated.
X-pessimism occurs in gate level designs when an X signal at the input causes the simulation output to be an X value, even though in real hardware the value will be deterministic. Figure 1 shows a very simple example. This is because in simulation, both X and ~X resolve to the value X. It is only when the data values are the same that it is determinate in real hardware. When the value of in1 and in2 are both 0, the simulation value at the output is 0, as it would in hardware. But when the “input” value is an X, and the values of in1 and in2 are both 1, the simulation value at the output is X in simulation but is 1 in real hardware. It is called X-pessimism because the known value simulates as an unknown.
X-pessimism occurs in gate level designs when an X signal at the input causes the simulation output to be an X value, even though in real hardware the value will be deterministic. To the right is a very simple example. This is because in simulation, both X and ~X resolve to the value X. It is only when the data values are the same that it is determinate in real hardware.
When the value of in1 and in2 are both 0, the simulation value at the output is 0, as it would in hardware. But when the “input” value is an X, and the values of in1 and in2 are both 1, the simulation value at the output is X in simulation but is 1 in real hardware. It is called X-pessimism because the known value simulates as an unknown.
Often the logic cone is very complex, Sometimes an output X value is a result of pessimism and sometimes it is simply the propagation of a real X. X-Pessimism can be artificially corrected without harm assuming the correction reflects the value driven by real hardware. It can be difficult to distinguish the real X versus the pessimistic X. Time consuming iterations between simulation and synthesis are required to debug and resolve differences. Unwarranted X-propagation proves costly, causes painful debug, and allows functional bugs to slip through to silicon.
Continued increases in SOC integration complexity and the interaction of blocks in various states of power management are exacerbating the X problem. While hardware resets can be used to initialize registers to known values, resetting every flop or latch is not practical because of routing overhead. Synthesis tools typically combine synchronous reset signals with data-path signals, thereby losing the distinction between X-free logic and X-prone logic.
This in turn causes unwarranted X-propagation during reset simulation. State-of-the-art low-power designs have additional sources of X’s due to switching between power modes. Verix SimFix is a next-generation product designed to correct pessimism at the netlist, ensuring that simulation results will match hardware behavior.
Netlist Static Analysis Reveals X-Issues
Mathematical methods are used to identify the conditions under which pessimism can occur in the design and the correct value for that set of conditions. Auxiliary files (SimPortal files) are then generated that can easily be used in simulation to accurately correct pessimism when it occurs, independent of the test sequence used.
- Efficiently identifies and corrects X-pessimism in netlist simulations
- Scales to meet growing demands of today’s SOCs
- Deterministic flow
- Minimal design knowledge needed
- Static analysis automatically partitioned across compute servers
- Uniform runtimes across partitions
- Optional monitors to show when X-pessimism correction is occurring.
- Low overhead in simulation (1.5x memory and 1.5x runtime)
- Supports block as well as full chip design sizes, and block level analysis can be used in full chip simulations
- Test independent
- Efficient gate-level simulations start quickly and painlessly so full-chip simulations are productive right away
- Shortens tape-out time
- Eliminates risk of inaccurate random initialization
- Eliminates overhead of pessimism-prevention synthesis options