Real Intent’s New Verix Product Family Delivers First Intent-Driven Multimode RTL Sign-off of SoC Designs
Brings New Levels of Innovation and Productivity to IC Design Teams through Enhanced Speed, Analysis, and Debug
Sunnyvale, Calif., USA, June 15, 2017
Real Intent, Inc., a leading provider of SoC and FPGA sign-off verification solutions, today announced its new Verix product family, and the introduction of the first complete multimode clock domain crossing (CDC) sign-off solution for RTL designs. The new Verix product family initially offers Verix CDC, which provides one-step analysis and debug of all operating modes in an IC, and boosts productivity for SoC and FPGA design teams. It also extends Real Intent’s product leadership in delivering the industry’s fastest performance, highest capacity, and most precise CDC solution in the market.
The Verix product family employs a new architecture for multimode analysis with Real Intent’s static intent verification technology. Repetitious single mode analysis is eliminated, so design teams can more quickly verify the correct operation of their designs and sign them off for implementation and manufacture. Additional Verix products will be introduced in the future that employ this new verification architecture.
Verix: Real Intent’s new product family for advanced multimode sign-off.
Verix CDC has additional enhancements for more precise RTL design analysis. In multimode analysis, it is imperative to interpret underlying clock intent in the design for accurate and low noise reporting. New static intent verification technology in Verix CDC automatically interprets whether clock interactions are possible or not within specific logic areas of the design. It automatically finds non-operational clock modes, and analyzes exclusive clock-regions to confirm correct circuit operation.
From a single Verix CDC analysis run, the iDebug visual debug product captures all the multiple modes for intelligent analysis of the design intent. It distinguishes the root cause for issues and provides guidance to quickly pinpoint the sources of problems. iDebug’s circuit visualization provides for easy investigation of design issues. With its powerful command line interface, iDebug supports a fully customizable sign-off methodology that can be tailored for any design flow. It also eliminates all data compromises, resulting in the most efficient debug process.
“The current single mode analysis method for clock domain crossing sign-off is a bottleneck for SoC and FPGA design teams,” stated Prakash Narain, Founder and CEO, Real Intent. “As the number of modes in a design continue to increase into the dozens, it is becoming nearly impossible to sign-off a design as changes affect other design modes and the need for continual re-runs. The design industry has already seen the success of multimode analysis for static timing sign-off. With Verix CDC, Real Intent is bringing multimode to clock domain crossing sign-off and saving design teams a tremendous amount of time and effort with an easy one-step set up and dramatically fewer iterations. Our customers are already reaping the benefits of this industry first product. We have seen over 3X savings in CPU time and 5X savings in engineering time per iteration. We look forward to bringing out more products in the Verix family in the coming months.”
For additional comments about the new Verix CDC, please view the video “Introducing Verix CDC” with Vikas Sachdeva, Senior Technical Marketing Manager at Real Intent:
For more information on Verix CDC, please visit the Verix CDC product page
Verix CDC is available now. Pricing depends on product configuration. For more information, please email email@example.com
About Real Intent
Real Intent is the industry leader in static sign-off of digital designs. Top-tier companies worldwide rely on Real Intent’s EDA software to accelerate early functional verification and sign-off at RTL as well as gate-level. Its intent-driven static technology powers solutions for clock and reset domain crossing analysis (CDC, RDC), Sign-Off quality clean RTL code, and X-pessimism correction, to ensure design success for SoCs and FPGAs. Real Intent products lead the market in performance, capacity and accuracy, enabling a measurably faster time to tape out. Please visit www.realintent.com for more information.
Real Intent and the Real Intent logo are registered trademarks, and Meridian is a trademark of Real Intent, Inc. All other trademarks and trade names are the property of their respective owners.
CDC: Clock-domain crossing
FPGA: Field programmable gate array
IC: Integrated circuit
RTL: Register transfer level