Comprehensive CDC Sign-off
In addition to metastability, clock domain crossings can introduce other catastrophic failures in the design.
Verix CDC comprehensively analyses clock/reset structures and identifies all possible CDC issues including incorrect or missing synchronization, glitch potential, reconvergence, structurally unsafe crossings, and potential data/control crossings that need functional verification.
Verix CDC supports Verilog, VHDL, and System Verilog languages and standard SDC or TCL format to read design constraints.
With Verix CDC, all CDC checks are enabled in multimode