Real Intent Unveils Major Performance Enhancements in Ascent IIV for Early Functional Verification of Digital Designs

SUNNYVALE, Calif. – February 26, 2014

– Real Intent Inc., a leading provider of EDA software products today announced a new version of its Ascent Implied Intent Verification (IIV) tool for early functional analysis of digital designs, delivering significant enhancements for users. Ascent products find elusive bugs and eliminate sources of uncertainty that are difficult to uncover using traditional Verilog or VHDL simulation, leading to both improved QoR and productivity of design teams.

New Ascent IIV features and enhancements include:

  • Improved root cause analysis minimizes time spent debugging FSMs
  • New FSM transition checks for deeper analysis of the design
  • New FSM debug reporting with direct trace back to state transition assignments
  • SystemVerilog 1800-2009 language support for easier adoption into existing design flows

Lisa Piper, senior manager of technical marketing at Real Intent, said, “The enhanced FSM checks and associated debug of IIV mean designers can find more bugs automatically without the need for any test benches. IIV’s root cause analysis dramatically reduces debug time by focusing the effort on the real design problems, without being distracted by related secondary issues. The enhancements we made to our SystemVerilog 2009 language support and file processing make it easier for design teams to adopt it into their existing design flows. Our Ascent products remain the fastest and highest-capacity verification solutions available for uncovering issues prior to digital simulation.”

To see a video interview about the new release of IIV and trends in automatic verification by Chris Morrison, chief architect at Real Intent, please click below

– Availability

The latest release of Ascent IIV is available immediately for download from the– Real Intent web-site.

About Ascent IIV

Ascent IIVis a state-of-the-art automatic RTL verification tool. It finds bugs using an intelligent hierarchical analysis of design intent. No test bench is needed, making it easy and efficient to find RTL bugs earlier in the design flow before they become more expensive to uncover. The analysis minimizes debug time by identifying the root cause of issues, and provides the VCD traces that show the sequence of events that lead to an undesired state. Ascent IIV has the speed and capacity to handle design blocks exceeding 250K gates and provides a wide variety of complex checks including FSM deadlocks, bus issues, and constant bits and nets. If SVA or VHDL assertions written in PSL are available, Ascent IIV can use these as constraints to enhance the analysis. Please click here for a recent announcement about how Real Intent’s Ascent IIV software accelerates design debug for a customer.

About Real Intent

Companies worldwide rely on Real Intent’s EDA software to accelerate early functional verification and advanced sign-off of electronic designs. The company provides comprehensive CDC verification, advanced RTL analysis and sign-off solutions to eliminate complex failure modes of SoCs. Real Intent’s Meridian and Ascent product families lead the market in performance, capacity, accuracy and completeness. Please visit for more information.


CDC: Clock Domain Crossing
EDA: Electronic Design Automation
FSM: Finite-State Machine
PSL: Property Specification Language
QoR: Quality of Results
RTL: Register Transfer Level
SoC: Systems-on-Chip
SVA: SystemVerilog Assertions
VCD: Value Change Dump
VHDL: Very High-level Design Language

Ascent and Meridian are trademarks of Real Intent, Inc.
All other trademarks and trade names are the property of their respective owners.