- NEC Adopts Real Intent Automatic Verification to Improve Design Quality
- Real Intent Unveils Major Performance Enhancements in Ascent IIV and Ascent XV Tools for early Functional Verification of Digital Designs
Early Verification Products
Ascent IIV is a state-of-the-art automatic RTL verification tool. It finds bugs using an intelligent hierarchical analysis of design intent. Since no testbench is needed, it is an easy and efficient method to find RTL bugs earlier in the design flow before they become more expensive to uncover. The analysis distinguishes the root cause for issues, and minimizes iterations and debug time.
- FSM deadlocks and unreachable states
- Bus contention and floating busses
- Full- and Parallel-case pragma violations
- X-value propagation
- Array bounds
- Constant RTL expressions, nets & state vector bits
- Dead code
- Uninitialized memory
Ascent IIV is unique for its smart reporting that distinguishes real issues from structural warnings, secondary errors and duplicate errors. Automatic VCD traces show the sequence of events that lead to an undesired condition and shows the time of failure. Ascent IIV supports integration with the industry-standard Verdi debugger from SpringSoft for the convenience of our users.
Ascent IIV supports the Verilog, VHDL, and System Verilog languages and provides early functional verification that automatically uncovers deep and fundamental bugs in RTL code.
- Exhaustive analysis quickly finds functional errors in early RTL
- Minimal effort required for fast results
- Smart reporting provides low noise results by distinguishing the root cause issues
- Debug starts earlier before simulation testing
- Early block level verification eliminates costly and lengthy chip-level simulation cycles