Real Intent Unveils Major Enhancements in Ascent XV for Early Detection and Management of Unknowns in Digital Designs
SUNNYVALE, Calif. – March 25, 2014
Real Intent Inc., a leading provider of EDA software products today announced a new release of its Ascent X-Verification System (XV) tool for early detection and management of unknowns (X’s) in digital designs, significantly enhancing optimization performance and debug reporting. All Ascent products find elusive bugs and eliminate sources of uncertainty that are difficult to uncover using traditional RTL simulation, leading to both improved quality of results (QoR) and productivity of design teams.
Ascent XV identifies X-sources and potential X-propagation issues early-on in Verilog RTL or netlist designs including X’s that occur during power-on initialization and switching between power modes. It enables debug of functional issues caused by X-optimism at RTL, prior to synthesis. It also eliminates unnecessary X’s caused by X-pessimism at the netlist level that make design debug difficult. Notable features for the new Ascent XV release include:
- 10X faster runtime in reset and retention-flop optimization that ensures complete initialization with minimal hardware and routing requirements, resulting in area and power savings
- Enhanced reporting of reset audit information and counts of X-sources for easier debug
- Greater integration with the Synopsys Verdi3 debug environment with new highlighting of X-sources and X-propagation on design schematics
- SystemVerilog 1800-2009 language support for even easier adoption into existing design flows
- Support for machines running the operating system SUSE Linux Enterprise Server 11 and above
“Analysis and optimization of design reset and initialization is a new requirement for SoC sign-off due to the presence of X’s that can arise from modern power-management techniques,” said Lisa Piper, senior manager of technical marketing at Real Intent. “Ascent XV can ensure that the initialization sequences are complete and optimal for various power states in an SoC and identify only those areas of risk that need attention by the designer, ignoring trivial X’s. With this new release we are continuing to innovate to deliver best-in-class verification performance and debug efficiency.”
Please see a video interview about the new release of XV by Lisa Piper below. To see a video interview of Pranav Ashar, CTO at Real Intent, about the need for X sign-off, please visit: our YouTube Channel . Real Intent also will make a presentation about Ascent XV at the VIA Developers Forum on Wednesday, Mar. 26, 2014; for details see: Press Releases.
The latest release of Ascent XV is available immediately for download from the Real Intent web-site.
About Real Intent
Companies worldwide rely on Real Intent’s EDA software to accelerate early functional verification and advanced sign-off of electronic designs. The company provides comprehensive CDC verification, advanced RTL analysis and sign-off solutions to eliminate complex failure modes of SoCs. Real Intent’s Meridian and Ascent product families lead the market in performance, capacity, accuracy and completeness. Please visit www.realintent.com for more information.
CDC: Clock Domain Crossing
CTO: Chief Technology Officer
EDA: Electronic Design Automation
RTL: Register Transfer Level
Ascent and Meridian are trademarks of Real Intent, Inc.
All other trademarks and trade names are the property of their respective owners.