X-Design and Verification System
The Ascent X-design and verification system (XV) prevents, detects and isolates issues caused by the propagation of unknowns (‘Xs’) in RTL designs, including Xs that occur during power-on initialization and switching between power modes. Early sign-off of X issues eliminates costly, painful gate-level debug, and prevents hidden functional bugs from slipping through to silicon.
The Unknown is Dangerous
The SystemVerilog standard defines an X as an “unknown” when simulation cannot definitely resolve a signal value. Due to simulation semantics, X’s can mask bugs in RTL simulation. While these bugs will still show up at the gate level, X-pessimism will cause additional X’s. Time consuming iterations between simulation and synthesis are required to debug and resolve differences. Unwarranted X-propagation thus proves costly, causes painful debug, and sometimes allows functional bugs to slip through to silicon. The comprehensive audit feature of Ascent XV exposes all X-sources, so you have a complete understanding of where problems might originate.
Low Power Challenges
Continued increases in SOC integration and the interaction of blocks with various states of power management are exacerbating the X problem. While hardware resets can be used to initialize registers to known values, resetting every flop or latch is not practical because of routing overhead. For synchronous resets, synthesis tools typically clump these with data-path signals, thereby losing the distinction between X-free logic and X-prone logic. This in turn causes unwarranted X-propagation during the reset simulation phase. State-of-the-art low-power designs have additional sources of Xs due to switching between power modes. Ascent XV is a next generation product designed to avoid, detect, and debug X-issues at RTL first, and to correct pessimism at the netlist.
Design Audit Reveals X Issues
Ascent XV delivers a comprehensive repost for determining how susceptible a design is to the masking of functional bugs and to unnecessary X’s. All X-sources in the design are automatically identified. The report shows nets in the design that are sensitive to X-optimism due to the propagation of an X from an X-source, and provides debug information with links to the source code and a trace from each net to an X-source in the design.
Power and Design Reset Optimization
Ascent XV ensures that X-issues are identified during transient power-states. Reset and retention optimization minimize block-level standby power and reduce reset routing complexity by assessing and then optimizing the number of flops that require hardware resets and/or retention cells to ensure a complete initialization. The report enables analyzing the initialization state of any power transition.
Debug X-issues with SimPortal
Ascent XV SimPortal generates an X-accurate model to detect and debug functional issues and to eliminate unnecessary X’s in the simulation environment. Assertion-based monitors on inputs and/or outputs of X-sensitive constructs quickly reveal the root cause of an error. Also, coverage monitors are provided to verify that all X-sensitive constructs have been exercised. Smart checkers ensure assumptions made in the analysis hold during simulation. A flexible X-verification testbench is generated that instantiates all of the SimPortal files so there is no need to touch the design testbench.
Powerful Debug Interface
Ascent XV comes with a powerful integrated graphical interface built around the Verdi™ Automated Debug System from Synopsys. It shows the path from the sensitive construct to an X-source, facilitates waivers of X-Sources and X-sensitive nets, and provides links from source code navigation.
- Minimize susceptibility to X-issues that mask functional bugs at RTL and cause unnecessary X’s in gate simulations
- Fast Design Audit identifies all X-source and X-sensitive constructs that X-source might propagate to.
- Reduces power and routing congestion through optimization of use of hardware resets and retention calls.
- SimPortal Verification automatically generates debug monitors and a simulation free of unnecessary X issues.
- Powerful integrated graphical interface built around the Verdi™ Automated Debug System from Synopsys.
- Debug monitors facilitate tracing issues back to the root cause.