Ascent XV

X-verification system
The Ascent X-Verification System (XV) detects and isolates issues with the propagation of unknowns (‘Xs’) in Verilog RTL. Early sign-off of X issues eliminates costly, painful gate-level debug, and prevents hidden functional bugs slipping through to silicon.

The Unknown is Dangerous
The SystemVerilog standard defines an X as an “unknown” value which is used when simulation cannot definitely resolve a signal to a “1”, a “0”, or a “Z”. Synthesis, on the other hand, defines an X as a “don’t care”, enabling greater flexibility and optimization. Unfortunately, Verilog RTL simulation semantics often mask propagation of an unknown value by converting the unknown to a known, while gate-level simulations show additional Xs that will not exist in real hardware. The result is that bugs get masked in RTL simulation, and while they show up at the gate level, time consuming iterations between simulation and synthesis are required to debug and resolve them. Resolving differences between gate and RTL simulation results is painful because synthesized logic is less familiar to the user, and Xs make correlation between the two harder. Unwarranted X-propagation thus proves costly, causes painful debug, and sometimes allows functional bugs to slip through to silicon.

Continued increases in SOC integration and the interaction of blocks in various states of power management are exacerbating the X problem. In simulation, the X value is assigned to all memory elements by default. While hardware resets can be used to initialize registers to known values, resetting every flop or latch is not practical because of routing overhead. For synchronous resets, synthesis tools typically clump these with data-path signals, thereby losing the distinction between X-free logic and X-prone logic. This in turn causes unwarranted X-propagation during
the reset simulation phase. State-of-the-art low power designs have additional sources of Xs with the additional complexity that they manifest dynamically rather than only during chip power up.

Design Audit Reveals X Issues
Ascent XV delivers a comprehensive report for determining how susceptible a design is to the masking of functional bugs and to unnecessary X’s. All X-sources in the design are automatically identified and classified as causing either optimism or pessimism. All associated X-sensitive nets are reported that are in the path of an X-source. A list of the inputs and outputs of each X-sensitive construct is also provided, along with debug information with links to the source code and a trace from each net to an X-source in the design.

Debug X-Issues with SimPortal
The SimPortal feature in Ascent XV generates an X-accurate model that can be used to detect and debug functional issues and to eliminate unnecessary X’s in the simulation environment. Assertion-based monitors on inputs and/or outputs of X-sensitive constructs quickly reveal the root cause of an error. Also, coverage monitors are provided to verify that all X-sensitive constructs have been exercised and smart checkers ensure assumptions made in the analysis hold during simulation. A flexible x-verification testbench is provided that instantiates all of the SimPortal files so there is no need to touch the design testbench.

Powerful Debug Interface
Ascent XV comes with a powerful integrated graphical interface built around the Verdi™ Automated Debug System from SpringSoft. It shows the path from the sensitive construct to an X-Source, facilitates waivers of X-Sources and X-sensitive nets, and provides links for source code navigation

Benefits

• Eliminate X-issues that mask functional bugs at RTL and cause unnecessary X’s in gate simulations
• Fast Design Audit identifies all X-sources and X-sensitive constructs in the design
• SimPortal Verification automatically generates a simulation free of unnecessary X issues.
• Powerful integrated graphical interface built around the Verdi™ Automated Debug System from SpringSoft
• Debug monitors facilitate tracing issues back to the root cause