Real Intent to Present Technical Seminar in Israel on Its RTL Sign-off and SoC Verification
SUNNYVALE, CALIF — Mar. 28, 2016
Real Intent, a provider of leading SoC and FPGA sign-off verification solutions
Will hold a day-long seminar in Israel packed with in-depth presentations and demonstrations about its advanced technologies for register transfer level (RTL) sign-off. Real Intent’s technical experts and an experienced user will speak about Real Intent’s Ascent™ and Meridian™ verification solutions that can help design engineers efficiently achieve successful sign-off of their SoC and FPGA designs. The seminar will cover such topics as:
- How to get sign-off confidence for CDC at the RTL
- Getting timing constraints right!
- Reducing verification debug cycle time with Lint & AutoFormal
- The X-propagation challenge
- New challenges in CDC — Crossing Glitches and Resets
Pranav Ashar, CTO, Oren Katzir, vice president of application engineering, and Menachem Bahat, application engineer, will cover Real Intent’s technical offerings for RTL sign-off and their productivity benefits for designers, and Uri Farkash, Israel sales manager, will serve as host for the event. Avihai Graizel, VLSI Team Leader at Valens Semiconductor will present technical information about their use of Real Intent’s technologies. To register, please visit: http://www.realintent.com/seminar
Real Intent’s best-in-class Ascent and Meridian products are the fastest, highest capacity, most accurate and complete verification solutions available for improving design team QoR and productivity. Ascent tools for early functional verification prior to synthesis find elusive bugs and eliminate sources of uncertainty that are difficult to uncover through traditional Verilog or VHDL simulation. Meridian products for advanced sign-off verification not possible with simulation or static timing analysis accelerate sign-off verification of clock domain crossings and timing constraints in in giga-gate SoC designs.
Tuesday, Apr. 5, 2016
9:15 to 16:00
at the Dan Accadia Hotel
Ramat Yam St 122, Herzliya, 46851, Israel
Phone: +972 9-959-7070
About Real Intent
Companies worldwide rely on Real Intent’s EDA software to accelerate early functional verification and advanced sign-off of electronic designs. Real Intent’s comprehensive CDC verification, advanced RTL analysis and sign-off solutions eliminate complex failure modes of SoCs, and lead the market in performance, capacity, accuracy and completeness. Please visitwww.realintent.com for more information.
Real Intent and the Real Intent logo are registered trademarks, and Ascent, Meridian and iDebug are trademarks of Real Intent, Inc. All other trademarks and trade names are the property of their respective owners.
CDC: Clock Domain Crossing
EDA: Electronic Design Automation
QoR: Quality of Results
RTL: Register Transfer Level
SoCs: Systems on Chip
VHDL: VHSIC High-level Design Language
VLSI: Very-Large-Scale Integration