Real Intent Sets a New Benchmark in Early Verification of Digital Designs with Release 2016.A of Ascent Lint

Revamped Frontend, more than 50 new rules and new database-driven debugger to boost productivity in complex SoC and FPGA design closure 

SUNNYVALE, CALIF — September 20, 2016

Real Intent inc., a leading provider of EDA software to accelerate functional verification and design sign-off, today announced significant enhancements to its Ascent Lint™. product, the industry’s fastest and most accurate tool for Lint verification of digital designs.

Real Intent’s Ascent products find design errors leading to improved quality of results and higher productivity for both design and verification engineers. The new 2016.A version of Ascent Lint significantly expands its coverage with more than 50 new customer-driven rules; it advances the Frontend with improved support of VHDL and System Verilog; and it provides a new database-driven debugger that offers unmatched productivity in delivering lint clean RTL.

Database-driven debug, provided by Real Intent’s new iDebug GUI and Command Line Interface, offers significantly more flexibility to users in addition to the text-based reporting. Ascent Lint 2016.A now comes with an integrated source browser and improved schematic visualization. It offers flexible searching, sorting, and waiving. Users can waive lint violations based on post analysis status without having to re-run lint analysis.

Over 50 customer-driven new rules have been added in this version of Ascent Lint. They span coding, compatibility, potential coding errors, synthesis issues, and more. New clock gating rules add significant value in the design of power aware RTL.

More enhancements include refinements to existing lint rules to reduce noise and faster compilation for Liberty files. Performance, capacity, and ease of use, the hallmarks of Ascent Lint strengths, have been further improved.

“Our customers developing next-generation FPGAs, reusable IP blocks, or complex SoCs require a linter that is fast, easy to use, and supports a comprehensive set of rules to support all stages of language based digital design,” said Jim Foley, R&D Director at Real Intent. “Our 2016.A Ascent Lint release sets a new benchmark in the market. Improved SystemVerilog and VHDL support and brand new ways of debugging lint issues provide a fast and productive way to prepare RTL designs for verification and implementation”

– Availability

Ascent Lint 2016.A is available now. Pricing will depend on the product configuration.

About Real Intent

Companies worldwide rely on Real Intent’s EDA software to accelerate functional verification and advanced sign-off of electronic designs. Real Intent provides comprehensive CDC verification, advanced RTL analysis and sign-off solutions to eliminate complex failure modes of SoCs. Real Intent’s Meridian and Ascent product families lead the market in performance, capacity, accuracy and completeness. Please visit for more information.


FPGA: Field-Programmable Gate Array
HDL: Hardware Description Language
RTL: Register Transfer Level
SoC: Systems-on-Chip
VHDL: VHSIC High-level Design Language

Real Intent and the Real Intent logo are registered trademarks, and Ascent, Meridian and iDebug are trademarks of Real Intent, Inc. All other trademarks and trade names are the property of their respective owners.