Real Intent Delivers Next Release of Meridian Constraints for Sign-Off of SoC Designs

Offers Unique Analysis and Debug, and Support for Distributed Development


Real Intent, Inc., a leading provider of SoC and FPGA sign-off verification solutions, today announced the next release of its Meridian Constraints product for comprehensive timing constraint verification and management. This software release adds new and unique functional analysis, data-driven debug and support for distributed design development, maintaining Real Intent’s product leadership in providing delivering the industry’s fastest sign-off solutions.

This latest version of Meridian Constraints provides new functional analysis of timing exceptions needed for untimed paths in logic designs, including false paths and multi-cycle paths. Untimed paths require separate verification that existing synthesis and static timing analysis tools do not validate. The newly added functional analysis accelerates the sign-off of timing exceptions by dramatically reducing by 50-percent the number of paths needing formal verification.

Today’s SoC designs are developed using IP blocks from third-party sources and geographically remote design teams. The sign-off for these IP blocks requires high-quality timing constraints early in the design development flow. Meridian Constraints verifies and propagates SDC at the block-level and promotes these constraints to the top-level of the design to ensure consistent specification of system timing and faster design sign-off.

Ramesh Dewangan, vice president of product strategy at Real Intent, explained, “Meridian Constraints meets the needs of design teams to create, manage, and verify all of their SDC timing constraints. It also ensures that constraints completely cover the design, correctly match the functional and timing goals, and are consistent between different blocks and levels in the design. Having correct and complete constraints and associated clock definitions ensures timing goals are met. Leveraging functional analysis capability with industry-leading formal analysis technology in Meridian Constraints gives users maximum confidence in the correctness of their exceptions, minimizing the risk of a re-spin due to bad exceptions that cause incorrect circuit operation.”

Meridian Constraints also includes iDebug, Real Intent’s new state-of-the-art design intent debugger and data manager. It employs a full database that captures all phases of SDC and CDC verification for the intelligent scope-based analysis of design intent. In addition, iDebug distinguishes the root cause for issues, and minimizes iterations and debug time through an easy-to-use programmable graphical interface. With its powerful command-line interface, iDebug supports a fully customizable sign-off methodology that can be tailored for any design flow.

Dewangan added, “Designers need to write SDC constraints based on timing goals for new IP and merge these with SDC constraints from existing or imported IP. Unfortunately, design teams often rely on spreadsheets and manual methods to organize this data. Meridian Constraints ensures their SDC is correct and consistent across the design hierarchy. Our new functional analysis tackles the challenge of quickly verifying the exceptions for untimed paths, for faster design sign-off. Meridian Constraints also enables correct clock domain crossing analysis, resulting in ultimate confidence for users, and successful low-power and X-verification flows.”

To see a video interview about SDC constraints management by Daryl Kowalski, technical marketing manager at Real Intent, please visit

Real Intent will demonstrate this new release of Meridian Constraints at its booth, #527, during the Design Automation Conference at the Austin Convention Center June 6 — 8, 2016.

– Availability

The new release of Meridian Constraints is available now. Pricing depends on product configuration. For more information, please email

About Real Intent

Companies worldwide rely on Real Intent’s EDA software to accelerate early functional verification and advanced sign-off of electronic designs. Real Intent’s comprehensive CDC verification advanced RTL analysis and sign-off solutions eliminate complex failure modes of SoCs and FPGAs, and lead the market in performance, capacity and accuracy, and provide a faster time to tape out. Please visit for more information.


CDC: Clock Domain Crossing
EDA: Electronic Design Automation
FPGA: Field Programmable Gate Array
IP: Intellectual Property
RTL: Register Transfer Level
SDC: Synopsys Design Constraints
SoC: Systems on Chip

Ascent, Meridian and iDebug are trademarks of Real Intent, Inc. All other trademarks and trade names are the property of their respective owners.