Meridian Constraints

Meridian Constraints
Comprehensive SDC Management and Verification
Meridian Constraints is the best in class, comprehensive design constraint management solution in the market. It offers high performance constraint validation, template generation, coverage analysis, equivalence checking and timing exception verification capabilities to provide users with the ultimate confidence in the timing constraints employed across all phases of the synthesis and implementation flow.
Timing constraints are used throughout the stages of digital design from synthesis through the implementation flow. At the pre-synthesis stage, timing budgets are established for each design block and then combined to create global constraints for the design. Further adjustment are made to timing constraints, post-synthesis, as the design is technology mapped and actual sign-off timing analysis can be done. After design implementation and routing additional timing data and updated constraints are then realized.

Meridian Constraints ensures the correctness, completeness and coverage of these timings constraints (SDC / TCL) as the design moves from RTL to implementation. Its state of the art formal engines verify all false or multi-cycle paths and eliminate incorrect timing exceptions that can mask silicon timing failure. To ensure completeness of timing constraints, coverage analysis uncovers where definitions are incomplete and features incremental generation capability to extend coverage for the design. Consistency between versions of timing constraints or between top-level and the block-level is assured with builtin equivalency checking.

Meridian Constraints verifies constraints in just minutes and can accelerate clock domain crossing (CDC) verification sign-off by ensuing correct and complete timing data is used. It provides automatic generation of constraints for false paths found in CDC. It is a natural complement to the Real Intent Meridian CDC verification tool.

Easy Adoption
Meridian Constraints is very easy to use. A single script reads in the design and constraint scenarios, either single or multi-mode, and performs all aspects of constraints management. Constraint validation pinpoints syntax, consistency and completeness issues of all design constraints including timing exceptions, which reduces iterations and speeds up higher quality implementation. Reports of violations are based on intelligent checks that reduce the total number to be reviewed and are more meaningful in comparison to other available tools. This makes validation easier and faster for designers.

Smart Reporting and Powerful GUI
Meridian Constraints smart reporting keep users focused on important issues through efficient organization of findings. The graphical user interface complements the smart reporting for fast debugging. Meridian Constraints has an integrated visualization tool. Pruned schematic views focus on fault-related logic, and with a few mouse clicks, users are directed to the RTL source code that caused the problem. The hierarchical debug approach allows for easy investigation deep into the design until the root cause is isolated.


  • RTL and gate-level constraint management
  • Incremental constraints template generation from a seed SDC file
  • Precise reporting from smart constraints checks
  • High performance engines with automatic incremental analysis
  • Fast debugging with cross probing to TCL/SDC, schematic, and design