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HCL: Connectivity & Glitch Verification Acceleration for VLSI Designs Using Static Methodology
Abstract:
Arun Selvaraju & Abhishek Ghate of HCLTech discuss their robust methodology for early checking of connection integrity at the RTL and netlist level for both the block and the top-level.
HCL used this methodology to successfully verify connectivity and glitches on an active SoC design using Real Intent’s SafeConnect in a few days, in contrast to several weeks work required with alternative methods.