Verix PCDC – Gate-Level CDC
Gate-level, Multimode, Clock Domain Crossing Sign-off
Verix Physical Clock Domain Crossing (PCDC) performs gate-level, multimode CDC sign-off, ensuring that all signals crossing from one clock domain to another asynchronous domain are reliably captured. The tool verifies that there are no issues with metastability, loss of correlation, or glitches.
Gate-level CDC verification is an important element of a complete CDC sign off flow, as RTL CDC verification assumptions may become invalid due to follow-on netlist-level changes from logic synthesis and power optimization steps.
- Logic synthesis may modify the CDC paths, such that the prior RTL CDC sign off is no longer valid.
- Power optimization may insert new logic elements that were not CDC-verified during RTL CDC sign off.
Additionally, rather than doing separate runs for each mode, Verix PCDC’s multimode clock domain crossing analysis allows all possible scenarios to be covered in a single run.
Because Verix PCDC fully leverages the Verix Multimode CDC RTL sign off data, the additional gate-level sign off step requires only an incremental effort from designers.
Netlist CDC Challenge
Netlist CDC requires significant set up effort as the RTL CDC constraints are not directly applicable to the netlist. Creating new constraints is duplication of effort, while manual conversion of constraints from RTL to Netlist is error-prone and needs high effort.
Gate-level analysis presents major capacity and scalability challenge. It is more difficult to identify CDC design structures like FIFOs due to expanded logic at gate-level. Debug is also a huge challenge at gate-level. Waivers at RTL level may not be applicable directly in netlist. It is also difficult to correlate netlist CDC paths with corresponding RTL paths.
RTL & Gate-level Clock Domain Crossing Divergence
CDC verification traditionally has been targeted at RTL sign-off before physical implementation begins. The CDC problems introduced during synthesis along with the addition of test logic and low-power optimizations are risk factors that have not been covered adequately until now.
The Verix PCDC software solution extends sign-off to the implementation stage. With the largest flat capacity of any tool in the industry, Verix PCDC provides verification without sacrificing precision.
It ensures a glitch-free implementation for all signal crossings, using the widest set of checks and the latest static analysis engines, including new high-performance formal engines. Implementation engineers can be confident the designs handed off to tape-out are free of CDC bugs. It leverages the results from RTL CDC to identify incremental CDC paths and constraints to optimize the CDC analysis at gate-level while providing maximum coverage.
Typical Implementation Errors
Implementation tools can introduce a number of potential hazards by failing to take CDC into account. Additional registers inserted by test synthesis, for example, can introduce new CDC paths not verified at RTL level.
Clock-gating cells inserted by synthesis tools to reduce switching power may also be incompatible with a good CDC strategy. Following a register, combinatorial cells, such as an AND gate, are sometimes used to pass a clock signal across the boundary. Such cells are likely to experience glitches.
Timing optimization can result in significant changes in logic organization. Faulty implementation of combinational logic may results in glitches on control and data path. The optimizer may choose also to clone flops so that the path following each flop has a lower capacitance to drive, which should improve performance. If the flops being cloned form part of a synchronizer, this can result in CDC problems. A better way of handling the situation is to synchronize the signal first, and then to duplicate the logic beyond the receiving synchronizer.
Typical CDC Glitch Failure at Gate Level
Smart Reporting and Powerful GUI
Verix PCDC’s smart reporting keeps users focused on important issues through efficient organization of findings. Helpful guidance and suggested actions help users pinpoint the source of the problems quickly. Real Intent’s state-of-the-art design intent debugger and analysis manager—iDebug—provides for user configurability and programmability with its command line interface (CLI). All the CDC analysis data is stored in a database that can be accessed through the CLI, so users are not stuck with one methodology that the tool provides for debug. Instead, users can create your own debug methodologies, custom to their own design flows which may include spreadsheet reports, graphical reports, scripting, and so on.
- Easy setup by reusing constraints from RTL
- Comprehensively verifies clock, control and data glitches in clock crossings
- Option for multi-core runs to reduce runtime significantly
- Easy to debug the crossing glitch issues, includes schematics and waveforms
- Incremental sign-off leveraging RTL CDC results
- Staged-formal analysis provides industry-leading throughput
- Full pathway for RTL + Netlist CDC sign-off
- Eliminates silicon risk by identifying CDC glitch failures
- Enables incremental sign-off through CDC-diff analysis
- Most precise CDC glitch reporting using integrated analysis
- Easiest-to-use CDC netlist solution in the industry
- Multiple technologies to enable complete glitch-free clock crossing sign-off at netlist