Verix DFT – Multimode Design for Testability

Datasheet

Multimode Design for Testability (DFT) Static Sign-off

Verix DFT is a high capacity, multimode DFT static sign-off tool, which runs a comprehensive set of DFT rules to rapidly identify RTL and gate-level design violations to help designers improve scan testability and coverage.

Verix DFT can be used for continuous DFT sign-off through completion of place & route:

  1. During RTL design — to fix asynchronous set/reset, clock and connectivity issues early.
  2. After scan synthesis — to check for scan chain rule compliance.
  3. Following place & route – to assess & correct issues with scan chain reordering or netlist modification.

Some of Verix DFT’s unique characteristics enable designers to prepare their RTL and gate-level designs for the highest possible quality ATPG pattern generation and silicon success.

  1. Multimode DFT, to check multiple sets of rules in a single run, reducing setup time, speeding up runtime, and accelerating debug.
  2. High capacity, to handle multimillion-gate designs in minutes with a low peak memory footprint
  3. Comprehensive, fine-grained rules, to ensure high coverage at all design stages and help accelerate debug and root cause analysis.
  4. Low noise, minimize false positives and error duplication
  5. Fast setup, which takes only hours instead of the weeks required with other DFT static tools.
  6. Fits easily with existing flows and DFT/ATPG tools.

Design for Testability

Continuous DFT static sign-off, beginning early in the RTL flow.

What is Design for Testability?

Design for Testability (DFT) refers to a design methodology that adds testability features to a hardware product design to enable application of manufacturing tests to the hardware.

Design for Testability includes: DFT static sign-off, which does structural & functional analysis of user-specified constraints & rules for scan testability; scan synthesis; embedded IP test wrapper insertion; and ATPG.

Multimode Reduces DFT Static Sign-off by Weeks

By checking multiple sets of rules in a single run, Verix DFT can reduce static sign-off time by several weeks.

There are three key aspects to Verix DFT’s multimode capabilities that reduce setup times, speed up runtime, and decreases the time spent debugging and fixing violations by generating one high-precision, organized report of all the test modes.

In a single multimode run, the tool can support:

1. Multiple ATPG partitions. Verix DFT saves substantial time by verifying multiple ATPG partitions in each run, eliminating the time-consuming process of running DFT static sign-off for each partition, with each partition requiring its own test mode.

2. Multiple constraint-sets. Verix DFT verifies design for testability sign-off rules for multiple sets of design constraints in one run. Each constraint set corresponds to the types of ATPG patterns — such as uncompressed, compressed, diagnostic, connectivity.

3. Multiple constraint-sets across multiple test modes. The combination of the first two capabilities gives designers the flexibility to verify multiple constraint-sets across multiple test modes, in a single run.

Multimode Design for Testability

Multimode DFT static sign-off reduces setup, runtime & debug

High coverage, Fine-grained Rulesets

High Coverage Rulesets

Real Intent Verix DFT has extremely high coverage rule sets to ensure robust analysis for:

  • Asynchronous Sets & Resets
  • Clocks
  • Scan chains
  • Individual flip-flops
  • Modules
  • Input/output ports
  • IEEE 1500 wrapper boundary to I/O port connectivity
  • General-purpose connectivity

Fine-grained Rules

Verix DFT splits general requirements into multiple fine-grained rules for accurate reporting and ease of debug.

The fine-grained rules accelerate debug and root cause analysis by allowing faster identification of specific, actionable design fixes. The rules can be applied in a global context as well as in the context of specific test modes for multimode runs.

One example of Verix DFT’s fine-grained rulesets are the ones for reset glitches, e.g. two different glitch sources converging and a glitch source re-converging with itself, with opposite polarity.

Another example is the fine-grained ruleset for lockup latches within scan chains:

Lockup latch is present

Lockup latch has correct enable signal

Lockup latch has correct polarity