Verix DFT – Multimode Design for Testability
Multimode Design for Testability (DFT) Static Sign-off
Verix DFT is a high capacity, multimode DFT static sign-off tool, which runs a comprehensive set of DFT rules to rapidly identify RTL and gate-level design violations to help designers improve scan testability and coverage.
Verix DFT can be used for continuous DFT sign-off through completion of place & route:
- During RTL design — to fix asynchronous set/reset, clock and connectivity issues early.
- After scan synthesis — to check for scan chain rule compliance.
- Following place & route – to assess & correct issues with scan chain reordering or netlist modification.
Some of Verix DFT’s unique characteristics enable designers to prepare their RTL and gate-level designs for the highest possible quality ATPG pattern generation and silicon success.
- Multimode DFT, to check multiple sets of rules in a single run, reducing setup time, speeding up runtime, and accelerating debug.
- High capacity, to handle multimillion-gate designs in minutes with a low peak memory footprint.
- Comprehensive array of rules, to ensure high coverage at all design stages.
- Fine rule granularity, to help accelerate debug and root cause analysis.
- Fast setup, which takes only hours instead of the weeks required with other DFT static tools.
What is Design for Testability?
Design for Testability (DFT) refers to a design methodology that adds testability features to a hardware product design to enable applying manufacturing tests to the hardware. Design for Testability includes: DFT static sign-off, which does structural & functional analysis of user-specified constraints and rules for scan testability; Scan Synthesis, which builds scan chains & DFT logic; and ATPG, which generates scan test vectors for manufacturing testing.
Multimode Reduces DFT Static Sign-off by Weeks
By checking multiple sets of rules in a single run, Verix DFT can reduce static sign-off time by several weeks.
There are three key aspects to Verix DFT’s multimode capabilities that reduce setup times, speed up runtime, and decrease the time spent debugging and fixing violations. In a single multimode run, the tool can support:
1. Multiple ATPG partitions. Verix DFT saves substantial time by verifying multiple ATPG partitions in each run, eliminating the time-consuming process of running DFT static sign-off for each partition, with each partition requiring its own test mode.
2. Multiple constraint-sets. Verix DFT verifies design for testability sign-off rules for multiple sets of design constraints in one run. Each constraint set corresponds to the types of ATPG patterns — such as uncompressed, compressed, diagnostic, connectivity.
3. Multiple constraint-sets across multiple test modes. The combination of the first two capabilities gives designers the flexibility to verify multiple constraint-sets across multiple test modes, in a single run.
Multimode DFT static sign-off reduces setup, runtime & debug
High coverage, Fine-grained Rulesets
High Coverage Rulesets
Real Intent Verix DFT has extremely high coverage rule sets to ensure robust analysis for:
- Asynchronous Sets & Resets
- Scan chains
- Individual flip-flops
- Input/output ports
- IEEE 1500 wrapper boundary to I/O port connectivity
- General-purpose connectivity
Verix DFT splits general requirements into multiple fine-grained rules for accurate reporting and ease of debug.
The fine-grained rules accelerate debug and root cause analysis by allowing faster identification of specific, actionable design fixes. The rules can be applied in a global context as well as in the context of specific test modes for multimode runs.
One example of Verix DFT’s fine-grained rulesets are the ones for reset glitches, e.g. two different glitch sources converging and a glitch source re-converging with itself, with opposite polarity.
Another example is the fine-grained ruleset for lockup latches within scan chains:
Lockup latch is present
Lockup latch has correct enable signal
Lockup latch has correct polarity
Lockup latch is redundant
Rule Selection & Configurability by Test Mode
Selectively Enable Rules
The rules can be selectively enabled in every test mode, such that the different test modes can each have different rules enabled.
This gives users the flexibility to do specific checking for different test modes, such as connectivity.
Configurable Rule Severity
Severity is also configurable by test mode. Design engineers can specify that one particular rule is an error in one test mode, while designating the same rule as only a warning or information-only in other test modes.
Rule severity configurable by test mode
Precise, Low Noise Violation Reports
Precise Violation Reports
Verix DFT produces a low noise violation report. The tool achieves this by executing accurate and detailed design analysis before reporting violations, thus more precisely reporting the violations per rule. Further, for each rule, there is no duplication when the violations are reported.
Tiered Violation Severity
Verix DFT organizes the violations in tiered priority order, providing guidance to help designers more quickly pinpoint the root cause.
The tiers are “errors”, “warnings” and “information-only”; the last tier allows designers to also provide useful information about the cells on each scan chain to designers. The rule severity can be set as appropriate.
Hierarchical Violation Categorization
Verix DFT’s violation reporting lets you hierarchically categorize the violations by:
- Rule — Specific violation types to check
- Tiered Rule Group — Rule violation instances grouped & categorized by test mode & severity level
- Policy/Violation Status — Container with multiple rule groups
Groups of related violations are shown in single report item. The group violations can then be toggled to expand or collapse.
For example, violations associated with a reset that was not disabled are grouped by a common reset source signal that drives all the violating flip-flops.
Debug: Custom Views & Waiver Tracking
Integrated debug, with custom views & cross probing
Real Intent’s integrated iDebug debugging platform provides schematics to facilitate DFT violation debugging. It enables:
- Custom views & cross probes to the RTL design source via a source browser or the integrated Emacs editor
- Easy waiving and other status tracking; the waivers can be ported between runs
Verix DFT also provides rule-specific debug information.
- Each Verix DFT rule violation contains information to assist with debugging. For example, for an incomplete scan chain, the tool provides the debug path, as well as the forward and back trace in/out points.
Root-cause Analysis & Guidance Accelerates Debug
Verix DFT provides precise, actionable reporting of violations, through multiple mechanisms, including:
- Labeling schematics with rule-specific debug information, such as labeling the glitch sources and the convergence instances in the schematic for reset glitch rule
- For path-based rule violations, listing the complete debug path from one end to the other
- Annotating test mode attributes on nets
- Creating customized report policies and filtering rule violations for additional precision
Verix DFT provides precise user instructions and guidance on set up changes required to fix specific violations. For example, it identifies and recommends the source of the clock root to be specified as a test clock.
Recommends test clock specification
Fault Coverage Estimation Option
Verix DFT has a fault coverage estimation option that estimates the fault coverage for each test mode to help the user prioritize the violation debug order and assess readiness for sign-off.
The report assesses the fault coverage for each test-mode, with a rollup of overall scan test fault coverage estimation.
The reports contain the counts and percentages for 1) total faults across all test modes and 2) total faults & testable flip-flops per test mode.