1. Multiple ATPG partitions. Verix DFT saves substantial time by verifying multiple ATPG partitions in each run, eliminating the time-consuming process of running DFT static sign-off for each partition, with each partition requiring its own test mode.
2. Multiple constraint-sets. Verix DFT verifies design for testability sign-off rules for multiple sets of design constraints in one run. Each constraint set corresponds to the types of ATPG patterns — such as uncompressed, compressed, diagnostic, connectivity.
3. Multiple constraint-sets across multiple test modes. The combination of the first two capabilities gives designers the flexibility to verify multiple constraint-sets across multiple test modes, in a single run.