Blog Archive
May 2012
5/08/2012: Gabe on EDA: Real Intent Helps Designers Verify Intent
5/07/2012: EDACafe: A Page is Turned
5/07/2012: Press Release: Graham Bell Joins Real Intent to Promote Early Functional Verification & Advanced Sign-Off Circuit Design Software
March 2012
3/21/2012: Press Release: Real Intent Demos EDA Solutions for Early Functional Verification & Advanced Sign-off at Synopsys Users Group (SNUG)
3/20/2012: Article: Blindsided by a glitch
3/16/2012: Gabe on EDA: Real Intent and the X Factor
3/10/2012: DVCon Video Interview: “Product Update and New High-capacity ‘X’ Verification Solution”
3/01/2012: Article: X-Propagation Woes: Masking Bugs at RTL and Unnecessary Debug at the Netlist
February 2012
2/28/2012: Press Release: Real Intent Joins Cadence Connections Program; Real Intent’s Advanced Sign-Off Verification Capabilities Added to Leading EDA Flow
2/15/2012: Real Intent Improves Lint Coverage and Usability
2/15/2012: Avoiding the Titanic-Sized Iceberg of Downton Abbey
2/08/2012: Gabe on EDA: Real Intent Meridian CDC
2/08/2012: Press Release: At DVCon, Real Intent Verification Experts Present on Resolving X-Propagation Bugs; Demos Focus on CDC and RTL Debugging Innovations
January 2012
1/24/2012: A Meaningful Present for the New Year
1/11/2012: Press Release: Real Intent Solidifies Leadership in Clock Domain Crossing
August 2011
8/02/2011: A Quick History of Clock Domain Crossing (CDC) Verification
July 2011
7/26/2011: Hardware-Assisted Verification and the Animal Kingdom
7/13/2011: Advanced Sign-off…It’s Trending!
May 2011
5/24/2011: Learn about Advanced Sign-off Verification at DAC 2011
5/16/2011: Getting A Jump On DAC
5/09/2011: Livin’ on a Prayer
5/02/2011: The Journey to CDC Sign-Off
April 2011
4/25/2011: Getting You Closer to Verification Closure
4/11/2011: X-verification: Conquering the “Unknown”
4/05/2011: Learn About the Latest Advances in Verification Sign-off!
March 2011
3/21/2011: Business Not as Usual
3/15/2011: The Evolution of Sign-off
3/07/2011: Real People, Real Discussion – Real Intent at DVCon
February 2011
2/28/2011: The Ascent of Ascent Lint (v1.4 is here!)
2/21/2011: Foundation for Success
2/08/2011: Fairs to Remember
January 2011
1/31/2011: EDA Innovation
1/24/2011: Top 3 Reasons Why Designers Switch to Meridian CDC from Real Intent
1/17/2011: Hot Topics, Hot Food, and Hot Prize
1/10/2011: Satisfaction EDA Style!
1/03/2011: The King is Dead. Long Live the King!
December 2010
12/20/2010: Hardware Emulation for Lowering Production Testing Costs
12/03/2010: What do you need to know for effective CDC Analysis?
November 2010
11/12/2010: The SoC Verification Gap
11/05/2010: Building Relationships Between EDA and Semiconductor Ventures
October 2010
10/29/2010: Thoughts on Assertion Based Verification (ABV)
10/25/2010: Who is the master who is the slave?
10/08/2010: Economics of Verification
10/01/2010: Hardware-Assisted Verification Tackles Verification Bottleneck
September 2010
9/24/2010: Excitement in Electronics
9/17/2010: Achieving Six Sigma Quality for IC Design
9/03/2010: A Look at Transaction-Based Modeling
August 2010
8/20/2010: The 10 Year Retooling Cycle
July 2010
7/30/2010: Hardware-Assisted Verification Usage Survey of DAC Attendees
7/23/2010: Leadership with Authenticity
7/16/2010: Clock Domain Verification Challenges: How Real Intent is Solving Them
7/09/2010: Building Strong Foundations
7/02/2010: Celebrating Freedom from Verification
June 2010
6/25/2010: My DAC Journey: Past, Present and Future
6/18/2010: Verifying Today’s Large Chips
6/11/2010: You Got Questions, We Got Answers
6/04/2010: Will 70 Remain the Verification Number?
May 2010
5/28/2010: A Model for Justifying More EDA Tools
5/21/2010: Mind the Verification Gap
5/14/2010: ChipEx 2010: a Hot Show under the Hot Sun
5/07/2010: We Sell Canaries
April 2010
4/30/2010: Celebrating 10 Years of Emulation Leadership
4/23/2010: Imagining Verification Success
4/16/2010: Do you have the next generation verification flow?
4/09/2010: A Bug’s Eye View under the Rug of SNUG
4/02/2010: Globetrotting 2010
March 2010
3/26/2010: Is Your CDC Tool of Sign-Off Quality?
3/19/2010: DATE 2010 – There Was a Chill in the Air
3/12/2010: Drowning in a Sea of Information
3/05/2010: DVCon 2010: Awesomely on Target for Verification
February 2010
2/26/2010: Verifying CDC Issues in the Presence of Clocks with Dynamically Changing Frequencies
2/19/2010: Fostering Innovation
2/12/2010: CDC (Clock Domain Crossing) Analysis – Is this a misnomer?
2/05/2010: EDSFair – A Successful Show to Start 2010
January 2010
1/29/2010: Ascent Is Much More Than a Bug Hunter
1/22/2010: Ascent Lint Steps up to Next Generation Challenges
1/15/2010: Google and Real Intent, 1st Degree LinkedIn
1/08/2010: Verification Challenges Require Surgical Precision
1/07/2010: Introducing Real Talk!

Fairs to Remember

Pranav Ashar   Dr. Pranav Ashar
   CTO of Real Intent

Real Intent participated in two events in Japan the last couple of weeks – EDSFair 2011 and Tokyo University Symposium. The followings are some of the highlights of the two events.

EDSFair 2011

EDSFair is a moderate size trade show for EDA companies held in Yokohama near Tokyo. Like DATE and DAC, it is accompanied by a parallel technical conference. It is an opportunity to network with electronic design companies in Tokyo, Osaka, Kyoto and some other nearby high-tech centers.

The show was held on Jan 27 and 28 (Thurs and Friday). The attendance was reasonable. In fact, the show looked quite busy post-lunch on Friday.

Real Intent got great traction at the show by exhibiting its leading edge software: Lint, Automatic Formal Verification, X-Verification, Clock Domain Crossing (CDC) verification, and Timings Constraints Management and Verification. In particular, the presentations on X-Verification and CDC verification were well received with many serious follow-ups.  Many attendees from large semiconductor companies seeking better solutions in the front-end verification space were very impressed with Real Intent’s high performance and high capacity Lint and CDC solutions which offer 10X improvement over competition. We got a lot of well qualified leads and it was a great show to start the year for Real Intent.

The next EDSFair will be held in October 2012 in conjunction with a semiconductor industry tradeshow so this was the last one held in the cold Japan winter. But it was well worth remembering.

Notes from Katsuhiko Sakano, General Manager of Real Intent K.K. in Japan

2011年1月27日(木)と28日(金)の両日、EDSフェアがパシフィコ横浜で開催されました。初日の午前中は来場者数も少なかったが

午後はセミナーの影響なのか、徐々に来場者数も増えてきました。2日目も同様で午後は徐々に来場者数も増えてきました。弊社ブースではCDCやX伝搬、SDC検証の問題を抱えている顧客が多く、とても良い話しができ、多くの顧客は評価を希望されています。昨年同様に日本のビジネス及びEDAビジネスも大変厳しい状況ですが、他社の皆さまと一緒に盛り上げて頑張りましょう。今年もご来場者200名以上の方々とお会いでき、とても感謝しています。来年も是非皆さまとお会いしましょう!

Tokyo University Symposium

The next stop after EDSFair was the “Advanced Design Methodology for VLSI Symposium” at Tokyo University graciously organized by Professor Masahiro Fujita. It was our privilege to participate. Tokyo University is a leading university in Japan and Prof. Fujita is a distinguished researcher in electronic design. 

The symposium brought together in one forum Real Intent with NextOp and SpringSoft. In my opinion, these three companies are the thought leaders today in advancing verification technology for the next generation of chips. 

NextOp presented its novel technology that finally makes available the automatic generation of assertions and functional coverage. SpringSoft presented new technologies for fast debug and verification closure. One of the ideas they presented had to do with mining the simulation output database in interesting ways for faster debug.

Real Intent gave the audience an  intuition and solutions for two verification problems that have become critical bottlenecks in the design flow: (1) the problem of X’s in simulation, and (2) the problem of verifying the humongous number of asynchronous interfaces on today’s chips. 

The program was led by a keynote by Maxeler Technologies on industrial-strength high-performance computing with an FPGA-based platform developed by the company.

All in all, the symposium was a very satisfying technical program that covered the state-of-art in high-end design, specification, implementation verification and debug. 

The audience consisted of faculty, students and electronic design professionals from local companies. Some of the companies in the audience were large design houses like Hitachi, Toshiba and Fujitsu as well as a number of smaller companies providing verification services, engineering recruitment and sales distribution. It was an excellent opportunity to network with the local professionals in terms of understanding their verification needs and projecting Real Intent as a key provider of enabling technologies for the verification of next-generation chips. 

The symposium finished on a high note with a drawing for an iPad. Appropriately, it was won by a student of Prof. Fujita’s.

Feb 8, 2011

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