Tradeshows and technical conferences serve as great places to survey the verification landscape and the Design Automation Conference in June was no exception.

EVE took the opportunity to poll visitors to its booth with a survey similar to the one used at EDSFair in Japan earlier in the year. Interestingly enough, some of our findings in the DAC survey tracked with findings from EDSFair. In some cases, they were widely dissimilar.

Our DAC attendees who took part in the survey included designers/engineers, managers, system architects, verification/validation engineers and EDA Tool Support or CAD managers.

Both sets of respondents noted that challenges are getting more complex as design teams merge hardware and software into systems on chip (SoCs). The Verilog Hardware Description Language (HDL) wins out as the number one language for both ASIC and testbench design, with SystemVerilog a distant second. DAC attendees ranked SystemC ahead of VHDL for ASIC design, while VHDL is used more than SystemC for testbench design.

Surprisingly, while more than 70% answered that they own between one and 100 simulation seats, 17% claimed to have more than 20 seats compared to only 12% between 100 and 200 seats. Our conclusion is that very large farms are more popular than large ones.

Unlike their counterparts at EDSFair, DAC attendees are less than satisfied with their current verification flow. Almost 70% of EDSFair attendees claim to be satisfied with their verification flow.

DAC attendees noted the same dissatisfaction for runtime performance and rated poorly the setup time for their verification flow. Also, efficiency in catching corner cases and reusability was ranked less than satisfied to fairly satisfied in both categories.

When asked to rate the importance of various benefits of a hardware-assisted verification platform when making a purchasing decision, they chose runtime performance, followed by price as most important. Visibility into the design and In-Circuit Emulation (ICE) came next. Compilation performance, simulation acceleration and transaction-based design, while considered important, received lower grades than the other criteria.

While simulation acceleration doesn’t rank highly in purchasing criteria, those surveyed claimed that simulation acceleration is the mode they use most for their hardware-assisted verification platform. ICE is listed as the second most used mode, and stand-alone emulation came in third. Few use it for transaction-based emulation. By comparison, the EDSFair survey revealed that transaction-based emulation was second after simulation acceleration and significantly more popular than stand-alone emulation and ICE.

The primary use for hardware-assisted verification is ASIC validation, with hardware/software co-verification a close second, a trend we also observed with EDSFair attendees and is most likely because of the move to include embedded software in SoCs.

Emulation can be used for hardware/software co-verification because it works simultaneously to verify the correctness of both hardware and embedded software. It can process quickly billions of verification cycles at high speeds. Unlike older generations that were prohibitively expensive, pricing for today’ emulators is competitive, a key consideration for EDSFair and DAC attendees.

The news from Japan in January was positive and I projected that the widespread adoption of hardware/software co-verification would be good for EDA’s verification sector in 2010. While the DAC survey didn’t offer up the encouraging signs, it did confirm that hardware/software co-verification is taking root. At EVE, we consider that a plus for the hardware-assisted verification market segment.

Jul 30, 2010