Blog Archive
July 2015
7/23/2015: Video: SoC Requirements and “Big Data” are Driving CDC Verification
7/16/2015: 50th Anniversary of Moore’s Law: What If He Got it Wrong?
7/09/2015: The Interconnected Web of Work
7/06/2015: In Fond Memory of Gary Smith
7/01/2015: Richard Goering and Us: 30 Great Years
June 2015
6/12/2015: Quick 2015 DAC Recap and Racing Photo Album
6/05/2015: Advanced FPGA Sign-off Includes DO-254 and …Missing DAC?
May 2015
5/28/2015: #2 on GarySmithEDA What to See @ DAC List – Why?
5/14/2015: SoC Verification: There is a Stampede!
5/07/2015: Drilling Down on the Internet-of-Things (IoT)
April 2015
4/30/2015: Reflections on Accellera UCIS: Design by Architect and Committee
4/23/2015: DO-254 Without Tears
4/17/2015: Analysis of Clock Intent Requires Smarter SoC Verification
4/09/2015: High-Level Synthesis: New Driver for RTL Verification
4/03/2015: Underdog Innovation: David and Goliath in Electronics
March 2015
3/27/2015: Taking Control of Constraints Verification
3/20/2015: Billion Dollar Unicorns
3/13/2015: My Impressions of DVCon USA 2015: Lies; Experts; Art or Science?
3/06/2015: Smarter Verification: Shift Mindset to Shift Left [Video]
February 2015
2/27/2015: New Ascent Lint, Cricket Video Interview and DVCon Roses
2/20/2015: Happy Lunar New Year: Year of the Ram (or is it Goat or Sheep?)
2/12/2015: Video: Clock-Domain Crossing Verification: Introduction; SoC challenges; and Keys to Success
2/06/2015: A Personal History of Transaction Interfaces to Hardware Emulation: Part 2
January 2015
1/30/2015: A Personal History of Transaction Interfaces to Hardware Emulation: Part 1
1/22/2015: Intel’s new SoC-based Broadwell CPUs: Less Filling, Taste Great!
1/19/2015: Reporting Happiness: Not as Easy as You Think
1/09/2015: 38th VLSI Design Conf. Keynote: Nilekani on IoT and Smartphones
December 2014
12/22/2014: December 2014 Holiday Party
12/17/2014: Happy Holidays from Real Intent!
12/12/2014: Best of “Real Talk”, Q4 Summary and Latest Videos
12/04/2014: P2415 – New IEEE Power Standard for Unified Hardware Abstraction
November 2014
11/27/2014: The Evolution of RTL Lint
11/20/2014: Parallelism in EDA Software – Blessing or a Curse?
11/13/2014: How Big is WWD – the Wide World of Design?
11/06/2014: CMOS Pioneer Remembered: John Haslet Hall
October 2014
10/31/2014: Is Platform-on-Chip The Next Frontier For IC Integration?
10/23/2014: DVClub Shanghai: Making Verification Debug More Efficient
10/16/2014: ARM TechCon Video: Beer, New Meridian CDC, and Arnold Schwarzenegger ?!
10/10/2014: New CDC Verification: Less Filling, Picture Perfect, and Tastes Great!
10/03/2014: ARM Fueling the SoC Revolution and Changing Verification Sign-off
September 2014
9/25/2014: Does Your Synthesis Code Play Well With Others?
9/19/2014: It’s Time to Embrace Objective-driven Verification
9/12/2014: Autoformal: The Automatic Vacuum for Your RTL Code
9/04/2014: How Bad is Your HDL Code? Be the First to Find out!
August 2014
8/29/2014: Fundamentals of Clock Domain Crossing: Conclusion
8/21/2014: Video Keynote: New Methodologies Drive EDA Revenue Growth
8/15/2014: SoCcer: Defending your Digital Design
8/08/2014: Executive Insight: On the Convergence of Design and Verification
July 2014
7/31/2014: Fundamentals of Clock Domain Crossing Verification: Part Four
7/24/2014: Fundamentals of Clock Domain Crossing Verification: Part Three
7/17/2014: Fundamentals of Clock Domain Crossing Verification: Part Two
7/10/2014: Fundamentals of Clock Domain Crossing Verification: Part One
7/03/2014: Static Verification Leads to New Age of SoC Design
June 2014
6/26/2014: Reset Optimization Pays Big Dividends Before Simulation
6/20/2014: SoC CDC Verification Needs a Smarter Hierarchical Approach
6/12/2014: Photo Booth Blackmail at DAC in San Francisco!
6/06/2014: Quick Reprise of DAC 2014
May 2014
5/01/2014: Determining Test Quality through Dynamic Runtime Monitoring of SystemVerilog Assertions
April 2014
4/24/2014: Complexity Drives Smart Reporting in RTL Verification
4/17/2014: Video Update: New Ascent XV Release for X-optimization, ChipEx show in Israel, DAC Preview
4/11/2014: Design Verification is Shifting Left: Earlier, Focused and Faster
4/03/2014: Redefining Chip Complexity in the SoC Era
March 2014
3/27/2014: X-Verification: A Critical Analysis for a Low-Power World (Video)
3/14/2014: Engineers Have Spoken: Design And Verification Survey Results
3/06/2014: New Ascent IIV Release Delivers Enhanced Automatic Verification of FSMs
February 2014
2/28/2014: DVCon Panel Drill Down: “Where Does Design End and Verification Begin?” – Part 3
2/20/2014: DVCon Panel Drill Down: “Where Does Design End and Verification Begin?” – Part 2
2/13/2014: DVCon Panel Drill Down: “Where Does Design End and Verification Begin?” – Part 1
2/07/2014: Video Tech Talk: Changes In Verification
January 2014
1/31/2014: Progressive Static Verification Leads to Earlier and Faster Timing Sign-off
1/30/2014: Verific’s Front-end Technology Leads to Success and a Giraffe!
1/23/2014: CDC Verification of Fast-to-Slow Clocks – Part Three: Metastability Aware Simulation
1/16/2014: CDC Verification of Fast-to-Slow Clocks – Part Two: Formal Checks
1/10/2014: CDC Verification of Fast-to-Slow Clocks – Part One: Structural Checks
1/02/2014: 2013 Highlights And Giga-scale Predictions For 2014
December 2013
12/13/2013: Q4 News, Year End Summary and New Videos
12/12/2013: Semi Design Technology & System Drivers Roadmap: Part 6 – DFM
12/06/2013: The Future is More than “More than Moore”
November 2013
11/27/2013: Robert Eichner’s presentation at the Verification Futures Conference
11/21/2013: The Race For Better Verification
11/18/2013: Experts at the Table: The Future of Verification – Part 2
11/14/2013: Experts At The Table: The Future Of Verification Part 1
11/08/2013: Video: Orange Roses, New Product Releases and Banner Business at ARM TechCon
October 2013
10/31/2013: Minimizing X-issues in Both Design and Verification
10/23/2013: Value of a Design Tool Needs More Sense Than Dollars
10/17/2013: Graham Bell at EDA Back to the Future
10/15/2013: The Secret Sauce for CDC Verification
10/01/2013: Clean SoC Initialization now Optimal and Verified with Ascent XV
September 2013
9/24/2013: EETimes: An Engineer’s Progress With Prakash Narain, Part 4
9/20/2013: EETimes: An Engineer’s Progress With Prakash Narain, Part 3
9/20/2013: CEO Viewpoint: Prakash Narain on Moving from RTL to SoC Sign-off
9/17/2013: Video: Ascent Lint – The Best Just Got Better
9/16/2013: EETimes: An Engineer’s Progress With Prakash Narain, Part 2
9/16/2013: EETimes: An Engineer’s Progress With Prakash Narain
9/10/2013: SoC Sign-off Needs Analysis and Optimization of Design Initialization in the Presence of Xs
August 2013
8/15/2013: Semiconductor Design Technology and System Drivers Roadmap: Process and Status – Part 4
8/08/2013: Semiconductor Design Technology and System Drivers Roadmap: Process and Status – Part 3
July 2013
7/25/2013: Semiconductor Design Technology and System Drivers Roadmap: Process and Status – Part 2
7/18/2013: Semiconductor Design Technology and System Drivers Roadmap: Process and Status – Part 1
7/16/2013: Executive Video Briefing: Prakash Narain on RTL and SoC Sign-off
7/05/2013: Lending a ‘Formal’ Hand to CDC Verification: A Case Study of Non-Intuitive Failure Signatures — Part 3
June 2013
6/27/2013: Bryon Moyer: Simpler CDC Exception Handling
6/21/2013: Lending a ‘Formal’ Hand to CDC Verification: A Case Study of Non-Intuitive Failure Signatures — Part 2
6/17/2013: Peggy Aycinena’s interview with Prakash Narain
6/14/2013: Lending a ‘Formal’ Hand to CDC Verification: A Case Study of Non-Intuitive Failure Signatures — Part 1
6/10/2013: Photo Booth Blackmail!
6/03/2013: Real Intent is on John Cooley’s “DAC’13 Cheesy List”
May 2013
5/30/2013: Does SoC Sign-off Mean More Than RTL?
5/24/2013: Ascent Lint Rule of the Month: DEFPARAM
5/23/2013: Video: Gary Smith Tells Us Who and What to See at DAC 2013
5/22/2013: Real Intent is on Gary Smith’s “What to see at DAC” List!
5/16/2013: Your Real Intent Invitation to Fun and Fast Verification at DAC
5/09/2013: DeepChip: “Real Intent’s not-so-secret DVcon’13 Report”
5/07/2013: TechDesignForum: Better analysis helps improve design quality
5/03/2013: Unknown Sign-off and Reset Analysis
April 2013
4/25/2013: Hear Alexander Graham Bell Speak from the 1880′s
4/19/2013: Ascent Lint rule of the month: NULL_RANGE
4/16/2013: May 2 Webinar: Automatic RTL Verification with Ascent IIV: Find Bugs Simulation Can Miss
4/05/2013: Conclusion: Clock and Reset Ubiquity – A CDC Perspective
March 2013
3/22/2013: Part Six: Clock and Reset Ubiquity – A CDC Perspective
3/21/2013: The BIG Change in SoC Verification You Don’t Know About
3/15/2013: Ascent Lint Rule of the Month: COMBO_NBA
3/15/2013: System-Level Design Experts At The Table: Verification Strategies – Part One
3/08/2013: Part Five: Clock and Reset Ubiquity – A CDC Perspective
3/01/2013: Quick DVCon Recap: Exhibit, Panel, Tutorial and Wally’s Keynote
3/01/2013: System-Level Design: Is This The Era Of Automatic Formal Checks For Verification?
February 2013
2/26/2013: Press Release: Real Intent Technologist Presents Power-related Paper and Tutorial at ISQED 2013 Symposium
2/25/2013: At DVCon: Pre-Simulation Verification for RTL Sign-Off includes Automating Power Optimization and DFT
2/25/2013: Press Release: Real Intent to Exhibit, Participate in Panel and Present Tutorial at DVCon 2013
2/22/2013: Part Four: Clock and Reset Ubiquity – A CDC Perspective
2/18/2013: Does Extreme Performance Mean Hard-to-Use?
2/15/2013: Part Three: Clock and Reset Ubiquity – A CDC Perspective
2/07/2013: Ascent Lint Rule of the Month: ARITH_CONTEXT
2/01/2013: “Where Does Design End and Verification Begin?” and DVCon Tutorial on Static Verification
January 2013
1/25/2013: Part Two: Clock and Reset Ubiquity – A CDC Perspective
1/18/2013: Part One: Clock and Reset Ubiquity – A CDC Perspective
1/07/2013: Ascent Lint Rule of the Month: MIN_ID_LEN
1/04/2013: Predictions for 2014, Hier. vs Flat, Clocks and Bugs
December 2012
12/14/2012: Real Intent Reports on DVClub Event at Microprocessor Test and Verification Workshop 2012
12/11/2012: Press Release: Real Intent Records Banner Year
12/07/2012: Press Release: Real Intent Rolls Out New Version of Ascent Lint for Early Functional Verification
12/04/2012: Ascent Lint Rule of the Month: OPEN_INPUT
November 2012
11/19/2012: Real Intent Has Excellent EDSFair 2012 Exhibition
11/16/2012: Peggy Aycinena: New Look, New Location, New Year
11/14/2012: Press Release: New Look and New Headquarters for Real Intent
11/05/2012: Ascent Lint HDL Rule of the Month: ZERO_REP
11/02/2012: Have you had CDC bugs slip through resulting in late ECOs or chip respins?
11/01/2012: DAC survey on CDC bugs, X propagation, constraints
October 2012
10/29/2012: Press Release: Real Intent to Exhibit at ARM TechCon 2012 – Chip Design Day
September 2012
9/24/2012: Photos of the space shuttle Endeavour from the Real Intent office
9/20/2012: Press Release: Real Intent Showcases Verification Solutions at Verify 2012 Japan
9/14/2012: A Bolt of Inspiration
9/11/2012: ARM blog: An Advanced Timing Sign-off Methodology for the SoC Design Ecosystem
9/05/2012: When to Retool the Front-End Design Flow?
August 2012
8/27/2012: X-Verification: What Happens When Unknowns Propagate Through Your Design
8/24/2012: Article: Verification challenges require surgical precision
8/21/2012: How To Article: Verifying complex clock and reset regimes in modern chips
8/20/2012: Press Release: Real Intent Supports Growth Worldwide by Partnering With EuropeLaunch
8/06/2012: SemiWiki: The Unknown in Your Design Can be Dangerous
8/03/2012: Video: “Issues and Struggles in SOC Design Verification”, Dr. Roger Hughes
July 2012
7/30/2012: Video: What is Driving Lint Usage in Complex SOCs?
7/25/2012: Press Release: Real Intent Adds to Japan Presence: Expands Office, Increases Staff to Meet Demand for Design Verification and Sign-Off Products
7/23/2012: How is Verification Complexity Changing, and What is the Impact on Sign-off?
7/20/2012: Real Intent in Brazil
7/16/2012: Foosball, Frosty Beverages and Accelerating Verification Sign-off
7/03/2012: A Good Design Tool Needs a Great Beginning
June 2012
6/14/2012: Real Intent at DAC 2012
6/01/2012: DeepChip: Cheesy List for DAC 2012
May 2012
5/31/2012: EDACafe: Your Real Intent Invitation to Fast Verification and Fun at DAC
5/30/2012: Real Intent Video: New Ascent Lint and Meridian CDC Releases and Fun at DAC 2012
5/29/2012: Press Release: Real Intent Leads in Speed, Capacity and Precision with New Releases of Ascent Lint and Meridian CDC Verification Tools
5/22/2012: Press Release: Over 35% Revenue Growth in First Half of 2012
5/21/2012: Thoughts on RTL Lint, and a Poem
5/21/2012: Real Intent is #8 on Gary Smith’s “What to see at DAC” List!
5/18/2012: EETimes: Gearing Up for DAC – Verification demos
5/08/2012: Gabe on EDA: Real Intent Helps Designers Verify Intent
5/07/2012: EDACafe: A Page is Turned
5/07/2012: Press Release: Graham Bell Joins Real Intent to Promote Early Functional Verification & Advanced Sign-Off Circuit Design Software
March 2012
3/21/2012: Press Release: Real Intent Demos EDA Solutions for Early Functional Verification & Advanced Sign-off at Synopsys Users Group (SNUG)
3/20/2012: Article: Blindsided by a glitch
3/16/2012: Gabe on EDA: Real Intent and the X Factor
3/10/2012: DVCon Video Interview: “Product Update and New High-capacity ‘X’ Verification Solution”
3/01/2012: Article: X-Propagation Woes: Masking Bugs at RTL and Unnecessary Debug at the Netlist
February 2012
2/28/2012: Press Release: Real Intent Joins Cadence Connections Program; Real Intent’s Advanced Sign-Off Verification Capabilities Added to Leading EDA Flow
2/15/2012: Real Intent Improves Lint Coverage and Usability
2/15/2012: Avoiding the Titanic-Sized Iceberg of Downton Abbey
2/08/2012: Gabe on EDA: Real Intent Meridian CDC
2/08/2012: Press Release: At DVCon, Real Intent Verification Experts Present on Resolving X-Propagation Bugs; Demos Focus on CDC and RTL Debugging Innovations
January 2012
1/24/2012: A Meaningful Present for the New Year
1/11/2012: Press Release: Real Intent Solidifies Leadership in Clock Domain Crossing
August 2011
8/02/2011: A Quick History of Clock Domain Crossing (CDC) Verification
July 2011
7/26/2011: Hardware-Assisted Verification and the Animal Kingdom
7/13/2011: Advanced Sign-off…It’s Trending!
May 2011
5/24/2011: Learn about Advanced Sign-off Verification at DAC 2011
5/16/2011: Getting A Jump On DAC
5/09/2011: Livin’ on a Prayer
5/02/2011: The Journey to CDC Sign-Off
April 2011
4/25/2011: Getting You Closer to Verification Closure
4/11/2011: X-verification: Conquering the “Unknown”
4/05/2011: Learn About the Latest Advances in Verification Sign-off!
March 2011
3/21/2011: Business Not as Usual
3/15/2011: The Evolution of Sign-off
3/07/2011: Real People, Real Discussion – Real Intent at DVCon
February 2011
2/28/2011: The Ascent of Ascent Lint (v1.4 is here!)
2/21/2011: Foundation for Success
2/08/2011: Fairs to Remember
January 2011
1/31/2011: EDA Innovation
1/24/2011: Top 3 Reasons Why Designers Switch to Meridian CDC from Real Intent
1/17/2011: Hot Topics, Hot Food, and Hot Prize
1/10/2011: Satisfaction EDA Style!
1/03/2011: The King is Dead. Long Live the King!
December 2010
12/20/2010: Hardware Emulation for Lowering Production Testing Costs
12/03/2010: What do you need to know for effective CDC Analysis?
November 2010
11/12/2010: The SoC Verification Gap
11/05/2010: Building Relationships Between EDA and Semiconductor Ventures
October 2010
10/29/2010: Thoughts on Assertion Based Verification (ABV)
10/25/2010: Who is the master who is the slave?
10/08/2010: Economics of Verification
10/01/2010: Hardware-Assisted Verification Tackles Verification Bottleneck
September 2010
9/24/2010: Excitement in Electronics
9/17/2010: Achieving Six Sigma Quality for IC Design
9/03/2010: A Look at Transaction-Based Modeling
August 2010
8/20/2010: The 10 Year Retooling Cycle
July 2010
7/30/2010: Hardware-Assisted Verification Usage Survey of DAC Attendees
7/23/2010: Leadership with Authenticity
7/16/2010: Clock Domain Verification Challenges: How Real Intent is Solving Them
7/09/2010: Building Strong Foundations
7/02/2010: Celebrating Freedom from Verification
June 2010
6/25/2010: My DAC Journey: Past, Present and Future
6/18/2010: Verifying Today’s Large Chips
6/11/2010: You Got Questions, We Got Answers
6/04/2010: Will 70 Remain the Verification Number?
May 2010
5/28/2010: A Model for Justifying More EDA Tools
5/21/2010: Mind the Verification Gap
5/14/2010: ChipEx 2010: a Hot Show under the Hot Sun
5/07/2010: We Sell Canaries
April 2010
4/30/2010: Celebrating 10 Years of Emulation Leadership
4/23/2010: Imagining Verification Success
4/16/2010: Do you have the next generation verification flow?
4/09/2010: A Bug’s Eye View under the Rug of SNUG
4/02/2010: Globetrotting 2010
March 2010
3/26/2010: Is Your CDC Tool of Sign-Off Quality?
3/19/2010: DATE 2010 – There Was a Chill in the Air
3/12/2010: Drowning in a Sea of Information
3/05/2010: DVCon 2010: Awesomely on Target for Verification
February 2010
2/26/2010: Verifying CDC Issues in the Presence of Clocks with Dynamically Changing Frequencies
2/19/2010: Fostering Innovation
2/12/2010: CDC (Clock Domain Crossing) Analysis – Is this a misnomer?
2/05/2010: EDSFair – A Successful Show to Start 2010
January 2010
1/29/2010: Ascent Is Much More Than a Bug Hunter
1/22/2010: Ascent Lint Steps up to Next Generation Challenges
1/15/2010: Google and Real Intent, 1st Degree LinkedIn
1/08/2010: Verification Challenges Require Surgical Precision
1/07/2010: Introducing Real Talk!

Video: SoC Requirements and “Big Data” are Driving CDC Verification

Graham Bell   Graham Bell
   Vice President of Marketing at Real Intent

Just before the design automation conference in June, I interviewed Sarath Kirihennedige and asked him about the drivers for clock-domain crossing (CDC) verification of highly integrated SoC designs, and the requirements for handling the “big data” that this analysis produces.  He discusses these trends and how the 2015 release of Meridian CDC from Real Intent meets this challenge.

He does this in under 5 minutes!   You can see it right here…



Jul 23, 2015 | Comments


50th Anniversary of Moore’s Law: What If He Got it Wrong?

Graham Bell   Graham Bell
   Vice President of Marketing at Real Intent

Electronics  April 16, 1965

Electronics April 16, 1965

On April 19, 1965, Electronics magazine published an article that would change the world. It was authored by a Fairchild Semiconductor’s R&D director, who made the observation that transistors would decrease in cost and increase in performance at an exponential rate. The article predicted the personal computer and mobile communications. The author’s name was Gordon Moore and the seminal observation was later dubbed “Moore’s Law.” Three years later he would co-found Intel. The law defines the trajectory of the semiconductor industry, with profound consequences that have touched every aspect of our lives.

The period is sometimes quoted as 18 months because of Intel executive David House, who in 1975 predicted that chip performance would double every 18 months; being a combination of the effect of more transistors and their faster switching time.

What if Gordon Moore got his math wrong and that instead of the number of components on an integrated circuit doubling every couple of years, he said every three years?

If we play out that scenario, we’d be back in 1998. The year Google was founded and Facebook’s Mark Zuckerberg was 14 years old. Apple discontinued development of the Newton computer, and Synopsys had just acquired EPIC and Viewlogic, and Cadence was buying Quickturn.  Intel had released the Pentium II microprocessor with around 8 million transistors in a 250nm process.  Here are some more consequences of a slower growth rate:

  • No modern smartphones (3.6 billion in use today)
  • No social media as we know it (Twitter started nine years ago when the New Horizons Pluto mission was launched)
  • Lower fuel efficiency and higher CO2 emissions
  • The World Wide Web was a youngster e.g. no YouTube
  • Lower agricultural output
  • Higher mortality rates
  • Renewable power would not be commercially viable e.g no solar panels on my house
  • China would not yet be the world’s manufacturing center

Fortunately(?), we live in 2015 and not 1998.  Moore’s law has continued to hold up after 50 years.  But like all exponential growth curves in the real world, they eventually saturate their eco-system and can grow no further.  Where are we with Moore’s law?

One positive sign is the announcement of 7nm test chips by IBM researchers.   The transistors were silicon-germanium channel types and extreme ultraviolet (EUV) lithography was used to fabricate the chips.  Designs employing 20 billion transistors will be possible.  Commercial availability is at least two to three years away.

According to Wally Rhines of Mentor Graphics, Moore’s Law is a special case of the engineering learning curve.  He says that as long as we could shrink feature sizes and wafer diameters fast enough, then we could stay on the learning curve. Sooner or later, we will have to do other things, because shrinking feature sizes will become too expensive. We will need to use other methods in addition to shrinking feature sizes to keep ahead.

And what will those other methods be?   That is a topic for another article.

Happy 50th Birthday to Moore’s Law!

Gordon Moore

Gordon Moore



Jul 16, 2015 | Comments


The Interconnected Web of Work

Ramesh Dewangan   Ramesh Dewangan
   Vice President of Application Engineering at Real Intent

“Imagine stepping into a car that recognizes your facial features and begins playing your favorite music. A pair of gloves that knows the history of your vehicle from the time of its inception as a lone chassis on the factory floor. “ –Doug Davis on IoT@Intel

Trends in the Internet of Things (IoT) has been fascinating to follow.

In my last blog on the topic I mentioned the 4 challenges facing an IoT system as spelled out by James Stansberry, SVP and GM, IoT Products, Silicon Labs: functionality, energy, connectivity and integration.

Four elements make up successful IoT hardware

Four elements make up successful IoT hardware

This had me thinking… Does this paradigm apply only to the hardware of IoT?

Let us look at a typical team in our workforce. The success of any work team depends on:

1. Skill set – This relates to functionality in the IoT diagram. Each team member brings unique skills (functionality) to the system. The team is successful only if you have the right mix of skills (is functionally complete).

wt-2In most EDA product development I have been involved in, we had an architect, a few software developers, some product engineers, a technical marketeer, a tech writer, and a build/regression owner and so on. Everyone in the team brought a unique set of skills to the table. Any time there was staff turnover and the loss of one specific skill, this caused the team output to suffer.

2. Energy – This term is especially relevant to work teams. Energy denotes the drive, enthusiasm and motivation of the people in their work together. The lower the energy of the people, the poorer the team performance will be. Likewise, poor energy efficiency and wasted power will not work for IoT. A high energy level (efficiency) is a key enabler for team success, and is also true for IoT hardware.

wt-3In one company that I worked for, we started as a highly energetic team excited about our engineering project, but as the management changed and the company grew larger, the energy started dwindling and the product took longer to ship. Great leaders detect this negative spiral and take corrective actions before it is too late.

3. Interaction  – This relates to Connectivity in the IoT diagram. The greater the synchronization of team members the higher the team output is. Likewise better connectivity enables IoT bandwidth and results. Just as infrequent and poor communication can bring a team performance to a crawl, poor connectivity can kill an IoT.

wt-4In one case, I had one of the smartest guys in the team, but wouldn’t get along with anyone else in the team. The conflict came to the point where the other team members began leaving the group. Our product delivery date was delayed by 6 months.

4. Integration – The same terminology applies to both teams and IoT. The more the team members integrate with each other, understand each other, have mutual trust and respect, the better the team performs. If team members are on different wavelengths, the team will perform poorly. Likewise, poor integration of IoT components will likely lead to a failued product.

I joined a Silicon Valley company with an international move to the United States. I was new to the culture and surroundings. In a team meeting, our Vice President told us he wanted team members to perform like Jerry Rice. I was astounded. I looked Jerry Rice up on the internet and figured out who he was. That was a poor way to integrate a diverse team.

I have tried to make the analogy that work teams (WT) and the internet-of-things both share the same components for success. If we understand why and how the work teams well, I think we can design better IoT systems! We better do this quickly, because IoTs are here to stay.

“If you think that the internet has changed your life, think again. The IoT is about to change it all over again!” — Brendan O’Brien, Chief Architect & Co-Founder, Aria Systems



Jul 9, 2015 | Comments


In Fond Memory of Gary Smith

Graham Bell   Graham Bell
   Vice President of Marketing at Real Intent

A long-time EDA industry analyst, Gary Smith, passed away on Friday, July 3, 2015 after a short bout of pneumonia in Flagstaff, Arizona.  He died peacefully surrounded by his family.

Gary Smith USNA graduate in 1963

Gary Smith in 1963

Gary was from Stockton, CA and graduated from the United States Naval Academy in 1963 with a bachelor of science degree in engineering.  His class yearbook says: “He managed to maintain an average grade point despite the frantic efforts of the Foreign Language Department. Tuesday nights found Gary carrying his string bass to NA-10 practice.”  Gary continued to be a musician and played his electric bass for years with the Full Disclosure Blues band at the Design Automation Conference Denali party with other industry figures.  The band started out of a jam session in 2000 with Grant Pierce who asked Gary to help put together a group for the following DAC.  Gary had suggested Aart de Gues as lead guitar who ended up giving the band its name.

Gary got into the world of semiconductors in 1969. He had roles at the following companies:

LSI Logic, Design Methodologist (and RTL evangelist), 2 years
Plessey Semiconductor, ASIC Business Unit Manager, 3 years
Signetics, various positions, 7 years

In 1994 he retired from the semiconductor industry and joined  Dataquest, a Gartner Company to become an Electronic Design Automation (EDA) analyst.  Gary described his retirement this way: “instead of having to worry about Tape Outs and Product Launches, I get to fly around the world and shoot off my big mouth (which I seem to be good at) generally playing the World’s Expert role. Obviously there isn’t much competition. Now if I could only get my ‘retirement’ under sixty hours a week I’d be happy.”

321270[1]In 2003, Gary had a health scare which was caught early and successfully treated.  Also around that time, he met his future wife Lori Kate.  I won’t share all the cute details of their story, but Gary’s charm eventually won her over, and they were married in July, 2004. They became the parents of a bouncing baby boy, Casey Carlisle Smith in Sept. 2005.

In late 2006 Gartner shut down Gary’s analyst group and he decided to reform under the name Gary Smith EDA. The only thing that changed according to Gary was all of the corporate stuff no longer interfered with his real work and finally got his work week down to 40 hours.

He was most recently a member of the Design TWG for the International Semiconductor Road Map (ITRS), editorial chair of the IEEE Design Automation Technical Committee (DATC) and served on the DAC Strategic Committee. He was also past Chair of the IEEE Electronic Design Processes conference. Gary has been quoted and published numerous times in all the electronics publications including EE Times, EDN, Electronic Business in addition to the Wall Street Journal and Business Week. In 2007, he received an ACM SIGDA Distinguished Service award.

Gary-headshot-180x220[1]Over the last 15 years, I personally enjoyed getting together with Gary each spring in anticipation of the upcoming DAC show to give him an update on what was new in the EDA products I was marketing.  Gary always listened politely and then gave his opinion on what he thought was going to work or not.  If Gary like what you were doing, your company was mentioned on his famous What to See @ DAC List.

I will miss Gary’s wit and insights and promotion of the electronic system level (ESL) for design.

To provide a loving memorial for his son Casey and granddaughters, Rachel and Shannon, his wife Lori Kate and the family kindly request that you share your favorite stories and/or pictures with memory@garysmitheda.com.

A memorial service is in planning for the late morning of Sunday, July 12th in San Jose, CA.  If you are able to attend please send an email with the size of your party so that the appropriate arrangements can be made.  All are welcome. To contact Lori Kate, please use memory@garysmitheda.com.



Jul 6, 2015 | Comments


Richard Goering and Us: 30 Great Years

Graham Bell   Graham Bell
   Vice President of Marketing at Real Intent

Richard Goering at his 30th DAC, San Francisco in 2014

Richard Goering at his 30th DAC, San Francisco in 2014

Richard Goering, the EDA industry’s distinguished reporter and most recently Cadence blogger is finally closing his notebook and retiring from the world of EDA writing after 30 years.  I can’t think of anyone that is more universally regarded and respected in our industry, even though all he did was report and analyze industry news and developments.

Richard left Cadence Design Systems at the end of June (last month).  According to his last blog posting EDA Retrospective: 30+ Years of Highlights and Lowlights, and What Comes Next he will be pursuing a variety of interests other than EDA. He will “keep watching to see what happens next in this small but vital industry”.

When Richard left EETimes in 2007, there was universal hand-wringing and distress that we had lost a key part of our industry.  John Cooley did a Wiretap post on his DeepChip web-site with contributions from 20 different executives, analysts and other media heavyweights.  Here are a just few quotes that I picked out for this post:

Richard was a big supporter of start-ups and provided the best coverage that this industry could ever get.

– Rajeev Madhavan of Magma

Richard has been a cornerstone of the EDA industry since I was on the customer side. He was never influenced by hype; he looked for content. I have always appreciated his objectivity, recognizing that his analysis would go beyond the superficial aspects of an industry event or product announcement and search for the real impact.

– Wally Rhines of Mentor

Goering has been an icon for the EDA industry since I first became aware of what EDA was. EDA is an industry with somewhat loose definitions. Just as you can say that RTL is defined by what Design Compiler accepts, you can say that EDA is defined by what Richard Goering covers. If he stops covering it, will it stop being EDA?

– John Sanguinetti

Like Rajiv Madhavan, I also experienced the great support of my startup back in 1999.  A few of us had founded a formal verification company called HDAC (later Averant) and we were very surprised to end up on the front-page of EETimes when we launched.  Richard was indeed THE reporter at the number 1 industry publication.

You will want to read Richard’s last blog post.  His retrospective covers

1985, CAE/CAD, Daisy, Mentor, Valid, Orcad, Gates-to-RTL, function verification, ESL, high-level synthesis, lawsuits, standards wars, DFM, brain drain, and Where is EDA Headed?

For the last 6 years, Richard’s steady hand has covered industry trends and developments on behalf of Cadence. Never one for hyperbole and exaggeration he was always been a good read.

Goodbye Richard.  You will be very much missed.



Jul 1, 2015 | Comments


Quick 2015 DAC Recap and Racing Photo Album

Graham Bell   Graham Bell
   Vice President of Marketing at Real Intent

This years Design Automation Conference in San Francisco was excellent!   You don’t have to take my word for it.  At the Industry Liaison Committee meeting for DAC exhibitors on Thursday June 11, the various members were in agreement that show traffic was up, and the quality of the customer meetings exceeded expectations.  Why is that?  It is in large part of due to the tremendous efforts of Anne Cerkel senior director for technology marketing at Mentor Graphics, who was the general chair for the 52nd DAC.

One innovation at this year’s show was opening the exhibitor floor at 10 am.  This made it more convenient to see the morning keynotes and also more flexibility in commuting to the show from around the Bay area.  I think you can expect to see this again at the next 53rd DAC show in Austin Texas.

Our two GRID racing car simulators was one reason the show was excellent for Real Intent.  We were able to draw a large crowd to our booth.  Budding race car drivers could challenge their friends and colleagues to a race and enjoy our license-to-speed verification solutions.  A special thank you to Shama Jawaid and the team at OpenText who was our partner for the license-to-speed promotion.

Here are some quick photos from the show for you to enjoy.

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race-1

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mom-twins

Our booth hostesses Crisca and Costina with their mother Chau

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Happy Booth Staff



Jun 12, 2015 | Comments


Advanced FPGA Sign-off Includes DO-254 and …Missing DAC?

Graham Bell   Graham Bell
   Vice President of Marketing at Real Intent

One trend we’re seeing in Asia is the number of FPGA design starts — now counting in the thousands. Getting a functionally correct design is the first goal for designers. It is easy to think that once that is achieved FPGAs can shipped out in finished products. But that’s not a robust model. For example, we have had customers with failures in the field due to a subtle timing change between FPGA part lots. Larger FPGA designs have grown in complexity, resulting in an amalgamation of disparate IP that can lead to clock domain challenges. A robust model for FPGA designs requires advanced signoff tools, a design flow that works easily with Xilinx and Altera tools, and support for high-reliability standards like DO-254. This is where Real Intent’s Meridian and Ascent products excel. For high-performance, our CDC and Lint tools provide the confidence design teams need, with unsurpassed verification and sign-off support.

Come visit us in Booth #1422 at DAC in San Francisco, June 8-10 to see our latest technical presentations. To choose your technical presentation click here.

Can’t attend DAC?  Check out some of our latest video interviews with Real Intent technologists or email us for a personal presentation to you or your team.

 



Jun 5, 2015 | Comments


#2 on GarySmithEDA What to See @ DAC List – Why?

Graham Bell   Graham Bell
   Vice President of Marketing at Real Intent

The last two weeks before the Design Automation Conference in San Francisco are a busy time.  For us marketeers, it has been called “our Superbowl.”  We want to get the word out that we have something new and important to show visitors to at our exhibit booth.  But there is more going on which I will mention after I talk about our booth activities.

Real Intent is number two on the GarySmithEDA What to See @ DAC list.   I know why we are number two on the list.  But I don’t want to give the secret away. If you know the reason, then please let everyone know in the comments section at the end of the blog.

Here are the quick titles for our technical presentation in our demo suites.

  • Ascent Lint with 3rd Generation iDebug Platform and DO-254
  • Meridian CDC for RTL with New 3rd Generation iDebug Platform
  • Ascent XV with Advanced Gate-level Pessimism Analysis
  • Accelerate Your RTL Sign-off
  • Hierarchical CDC Analysis and Reporting for Giga-gate Designs
  • Next-Generation Meridian Constraints for SDC
  • Autoformal RTL Verification
  • FPGA Sign-off and Verification

Click on this appointment sign-up link to arrange a meeting with us.

Besides fast RTL sign-off, we are also having fun at our booth and giving away cool prizes.  Come and race against other drivers in our two GRID Racing Simulators and receive your License-to-Speed.   Get your license stamped at both the Real Intent and Open Text booths (just around the corner) and you will get a change to win $$$ Amazon gift cards.  Fill out our verification survey and you will get a chance to win a Roku 3 streaming media player or a Kindle PaperWhite e-reader.  Here is a picture of the GRID simulators.

SEGA-Grid-42-monitor

I hinted earlier that there was more going on than just activities at the Real Intent booth.  We are organizers for a Test and Verification panel:  Scalable Verification: Evolution or Revolution? on Wed., June 10 from 4:30-6 p.m. in Room #304. Moderated by Brian Bailey (technology and EDA editor of Semiconductor Engineering), it has a panel of experts from Freescale Semiconductor, NVIDIA, Qualcomm, Hewlett-Packard and ARM.

We are also sponsoring the Love IP DAC Party on Monday, June 8 at Jillians in the Metreon, just steps away from the Moscone Center. Doors open at 7 p.m. The party is organized by Heart of Technology (HOT), the philanthropic organization founded by EDA veteran Jim Hogan. This event brings the DAC and IP communities together to raise money for the San Jose State Guardian Scholars – a program to help underprivileged and homeless students at the university. The party’s theme is “Summer of Love,” so come in your best Jerry Garcia look-alike costume!

And don’t forget the The Denali Party by Cadence on Tuesday night, June 9.  You will want to sign up online before the DAC show starts to get your ticket by Tuesday morning.  See you there!



May 28, 2015 | Comments


SoC Verification: There is a Stampede!

Graham Bell   Graham Bell
   Vice President of Marketing at Real Intent

Red River Cattle DriveIn the stories of the Wild West from the 1800s, the image of a cattle drive often is depicted. A small team of cowboys delivers thousands of heads of cattle to market. The cowboys spend many days crossing open land until they reach their destination – one with stock yards to accept their precious herd, and a rail station to deliver it quickly to market. Along the way there are dangers, including losses by predators and mad stampedes by cattle rushing blindly when frightened or disturbed. The primary job of the cowboys is to keep the herd on track and settled as they move to ship-out.

I see immediate parallels between the cowboys of the Wild West and today’s system-on-chip (SoC) design and verification engineers. Cowhands struggle to control and move a big herd. Similarly, today’s design teams grapple with how to keep a project on target and converging to tape-out and success when the gate count of SoCs has become so large it can stretch and even overwhelm their ability to stay on track. How big are these new SoCs?

The Xbox One gaming console, for example, uses 5 billion transistors, which is equivalent to 1.25 billion digital gates. Its AMD-designed SoC produced at TSMC on a 28-nm process combines eight Jaguar CPU cores and Graphics Core Next (GCN)-class integrated graphics. (See Figure 1.)

soc-stampede-real-talk

nvidia_kepler2_die_shot-200Another example, pictured on the left, is Nvidia’s GK110 GPU (also made on TSMC’s 28-nm process), which has 7.1 billion transistors. This translates to nearly 2 billion digital gates. These are not just big chips but giant chips!

With each smaller semiconductor node foundries provide, more gates can be squeezed into the same die size. In parallel, many different kinds of design blocks and intellectual property (IP) are employed, usually created by third-parties, to accelerate the implementation of the design objectives. The interaction of the various blocks across various power and timing conditions adds a new kind of complexity to the design. The result is a “herd” of interfaces with thousands of different crossings that must be checked and verified to ensure the design does not run off into a fatal operating condition.

It would be great to have the luxury of several hundred design and verification engineers to verify all possible failures in these giant SoCs, but that is not usually the case. Typically a small team relies on design automation software to manage the complexity of the verification challenge.

For each interface in the SoC, signals cross asynchronously between the various IPs and must be registered correctly to ensure the integrity of the digital signal path and eliminate metastability errors. For bus-level signals, circuitry such as a FIFO manages the data transfer and verification to ensure there is no data overflow or underflow that could compromise the design. This approach requires a full-chip clock domain crossing (CDC) analysis.

Design teams need three elements to achieve overnight CDC analysis runs for functional sign-off – precision, throughput and ease of use. (See Figure 2.)

Precise analysis means the software must accurately capture all possible interfaces in the design, including buses; provide reset analysis, including glitches in both asynchronous and synchronous domains; and correctly handle crossings that may be blocked by environment definition. Once the analysis is done, it is essential to be able to verify the interfaces automatically, using formal technologies, so all possible failure conditions can be exhaustively covered.

Likewise, throughput has three important considerations:  runtime, capacity and methodology. Design analysis must be done in overnight runs to make the necessary progress to stay on schedule. In terms of capacity, a terabyte of computer memory no longer is needed to verify a 500-million gate design. Instead, teams can use more standard hardware. For giga-scale designs, a hierarchical methodology is needed to leverage block-level CDC signoff for chip-level CDC verification. This methodology is effective for sign-off only if the SoC verification makes no approximations or abstractions. Only then can it truly ensure no signal crossing errors are missed.

Ease of use is the third major aspect of CDC analysis for functional sign-off. The software setup must be easy and automated to ensure the quality of results. The various kinds of analysis including formal analysis must generate results without the user writing any tests. Finally and perhaps most important, the debug of analysis results must be hierarchical and fully customizable. This kind of flexibility is available typically only from a full database of analysis results. Graphical and command-line interfaces must be able to extract the necessary reports in a variety of formats and with the data organized as required for any specific verification flow requirements. Whether using HTML docs or custom spreadsheets, the design and verification team should be able to “rope-in” any interface issue.

SoC-Stampede-Fig-2-620px

SoC verification poses many challenges through the sheer size of designs and the various mix of design IP, each operating with its own clocking scheme. Successful SoC design teams will meet the challenge of clock domain crossing verification with a solution that provides the necessary precision, throughput and ease-of-use they need. This approach will avoid a stampede of errors and late debugging that will delay the ship-out of their designs.


 

This blog article was originally published on EETimes SoC Designlines.

 



May 14, 2015 | Comments


Drilling Down on the Internet-of-Things (IoT)

Ramesh Dewangan   Ramesh Dewangan
   Vice President of Application Engineering at Real Intent

Did you know there will be 50 billion connected devices by 2020?

I am not making it up!

This was the future painted by Dr. Martin Scott, SVP and GM, Cryptography Research Division, Rambus, in a scintillating session on the Internet of Things (IoT) at the Silicon Summit 2015 event organized by Global Semiconductor Alliance in April.

What will the future look like when there will be more than six devices for every person on the planet?

I’ll summarize what I learned regarding three IoT topics: the components, the scope and the challenges.

Components of an IoT System

Dr. Scott laid out the high-level components of an IoT system:

  • End points are the IoT devices with sensors, hardware and software to provide touch point to the users or gather data
  • The Hub/Edge is the data gateway or aggregator. It could be a group of mobile phones, routers, towers and so on.
  • There is a cloud system/data center to store and analyze data. A high bandwidth wide area and local area connectivity move data from the end points to the Hub and data center.

 

Fig. 1 Components of an IoT System

Fig. 1 Components of an IoT System

Lastly you have Analytics apps to provide meaningful data back to the providers and consumers.

Scope of IoT

The scope of IoT applications is vast. I was aware of its applications in the consumer segment based on media coverage that I had seen previously. It turns out that in addition to the consumer segment, IoT is already playing major roles in industrial and medical segments. As per Rahul Patel, SVP and GM, Wireless Connectivity, Broadcom, IoT has limitless possibilities.

 

Fig. 2 Example applications of IoT across three categories

Fig. 2 Example applications of IoT across three categories

Challenges to IoT success

James Stansberry, SVP and GM IoT Products, Silicon Labs laid out the challenges succinctly: Energy, Functionality, Integration and Connectivity.

Energy: How many times have you been frustrated with your smart phone running out of juice in the middle of the day? While devices are improving battery life with every generation, IoT devices need sustained battery life for a much longer period. IoT devices must operate on a coin cell battery for five years. Unless that happens, the applications will be limited. The SoCs driving the IoT devices have to be ultra-low power.

Connectivity: The bandwidth and flexibility of existing connectivity systems, be they WiFi, Bluetooth or LTE, are too limiting for IoTs to become pervasive. There needs to be higher bandwidth and flexible switching among the connectivity protocols. New standards like new WiFi standards, Bluetooth Smart, ZigBee, and THREAD are emerging as viable solutions.

Integration: A typical IoT SoC will need to integrate highly complex IP and interface with sensors, control, RF and batteries. The process nodes and the SoC development methodology must enable such large-scale integration.

 

Fig. 3 Hardware Components of an IoT Device

Fig. 3 Hardware Components of an IoT Device

Functionality: Dr. Scott pointed out that sensitive data in transit remains vulnerable going from end-point to hub to cloud. The functionality must include security as a key component.

PERSONAL EXPERIENCE

Recently, my son realized that he had lost his car keys at his college campus one weekend. I thought he would be frantic, asking around for help to find them. Instead, he calmly opened an app on his smart phone and then located his keys on a convenient map, thanks to a tiny tracking chip he had added to his key ring.

IoT is not a concept anymore; it is real, and it is happening. It will become pervasive and ingrained in our lives as soon as the significant challenges in functionality, energy, connectivity and integration are tackled!



May 7, 2015 | Comments