Real Intent on DeepChip’s Cheesy List for DAC 2017
Real Intent on this year’s Cheesy List:
Real Intent Meridian CDC does new transparent hierarchical models for separate CDC analyses at unit-level. New consistency checks across chip hierarchy. On 300M gate chip with 103 clock domains, the hierarchical CDC runtime cut by 5X and memory use cut by 4X. (booth 928) Ask Vikas Sachdeva. Freebie: cellphone batteries
NEW! — Real Intent Verix Multimode CDC is a “brand new tool for true multi-mode CDC RTL analysis.” Single set-up. All modes in single run, no iterations. New static intent verification finds non-operational clock modes. Vs. Spyglass or Questa, it saves 3.3x CPU time and 5x engineering time per iteration. See ESNUG 574 #2. (booth 928) Ask Vikas Sachdeva. Freebie: cellphone batteries
Real Intent Ascent XV does X-propagation checks. Ranks X-sources and X-sensitive nets by failure importance. Initialization audits. Setup-free X-pessimism analysis at gate-level with only 3X overhead versus 5x-10X from other tools. Now goes deeper; found a gate-level Xs in a 220M gate design. Replaces using VCS/Incisive/Questa’s X-safe simulation switches. Finds minimally correct reset schemes.
(booth 928) Ask Lisa Piper. Freebie: cellphone batteries
NEW! — Real Intent Meridian RDC finds reset configurations and complex reset interactions, not covered by existing tools. Finds reset metastability and glitch problems. Optimized data models. 200M gate full chip RDC analysis in 9 hrs with ~160 G memory.
Join Real Intent at DAC as we Unveil our Revolutionary Multimode Sign-off Solution!
|You are invited to visit Real Intent in booth #928 at the 54th DAC show in Austin|
|Real Intent is known for having the fastest, highest-capacity verification tools for early functional verification and advanced RTL sign-off.
Real Intent is making major announcements at DAC:
Real Intent unveils Verix CDC!
Verix CDC is a revolutionary first-to-market multimode CDC solution. Built on proprietary static-intent technology, Verix CDC keeps pace with the multimode sign-off requirements posed by the increasingly complex system-level nature of the modern SoC. Verix CDC delivers an order of magnitude reduction in the CDC sign-off effort for today’s SoCs by simplifying setup and reducing the need to duplicate reviews.
Real Intent expands its sign-off portfolio!
Real Intent proudly announces Meridian RDC, a brand new product that is the most precise Reset Domain Crossing tool available to reduce the insidious silicon risk associated with resets. Together with our Meridian CDC sign-off product, it covers the full complement of failures caused by metastability in the modern SoC.
Real Intent’s market-leading Meridian CDC has been upgraded with the addition of a hierarchical CDC flow based on proprietary transparent hierarchical models that deliver scale along with our trademark precision and comprehensiveness.
Finally, Real Intent is showcasing Ascent XV Pessimism, a field-tested new product for automatic X-pessimism correction in gate-level simulation, delivering the scale and efficiency that make full-chip gate-level simulation viable with all the major simulators. With gate-level simulation widely adopted as an essential backstop in sign-off, Ascent XV Pessimism saves months of sign-off effort.
Come see how Real Intent has taken a leap forward with these new advances!
Our technical presentations will bring you up to date with our new product releases that have been proven on giga-gate SoC and FPGA designs. Visit our DAC page to book your appointment with Real Intent at booth #928.
|Introducing Verix CDC: Industry’s most precise multimode CDC solution specially architected for multimode analysis with static intent verification|
|Real Intent introduces Verix CDC, the revolutionary and most precise multimode CDC solution in the market. Verix CDC performs comprehensive CDC analysis using multiple clocks reaching the flops, so all possible scenarios are covered in a single run. It is built on a specialized static intent technology that interprets clock intent and enables the most comprehensive clock intent management and multimode CDC sign-off. The result is a manifold reduction in the CDC sign-off effort for today’s SoCs. Schedule a Time.|
|Accelerate Your RTL Sign-off|
|Real Intent will present the elements of a best-in-class solution for the accelerated RTL sign-off of SoC and FPGA designs. A full suite of static verification tools will be covered including: RTL static and formal intent verification, reset analysis and optimization, CDC sign-off, RDC sign-off, and X-safe design analysis. Schedule a Time.|
|Most precise static and formal RTL Analysis with Ascent Lint and AutoFormal|
|Ascent Lint, together with AutoFormal, continues to be the industry’s fastest and lowest-noise RTL functional verification solution. We will present the latest advances including support for VHDL 2008 and SystemVerilog 2012, and the new integrated debugger. Come hear about the latest new linting rules and how new advances in Automatic Formal yields higher capacity and performance than ever before. Schedule a Time.|
|Meridian CDC with Hierarchical CDC flow|
|Meridian CDC continues to be the fastest, highest capacity and most precise CDC sign-off solution in the market. At DAC 2017, we present the industry’s best Hierarchical CDC capability that allows users to perform CDC verification on billion-gate SOCs within a matter of hours. The flow enabled by transparent model database provides unprecedented productivity gains, high accuracy, low noise results with seamless SoC debug. You will not want to miss seeing the latest in advanced CDC sign-off. Schedule a Time.|
|Ascent XV with Advanced Gate-level Pessimism Analysis|
|Ascent X-Verification System (XV) provides a comprehensive static solution for making an RTL design X-robust and eliminates error-prone debug at the netlist level. At DAC, discover the very latest in X-propagation verification. See how to identify unnecessary resets at RTL. Learn a cost effective approach for tackling pessimism accurately in your gate level simulations. Schedule a Time.|
|Introducing the industry’s most accurate Reset Domain Crossing solution|
|Meridian RDC is the lowest noise and most precise reset domain crossing sign-off tool in the market. It performs efficient and thorough static analysis to ensure that signals crossing reset domains function reliably. Among other things, it identifies metastability problems arising from software and/or low power resets. Meridian RDC is the only solution that considers cascading effects of improper reset design and enables comprehensive reset domain crossing sign-off. Schedule a Time.|
|Gate-Level CDC Sign-off with Meridian Physical CDC|
|RTL CDC sign-off assumptions may not be valid because of logic synthesis and power optimizations. Meridian Physical CDC is the only solution that ensures complete gate-level sign-off. See how a new architecture leverages results of RTL CDC sign-off and performs efficient and incremental CDC analysis at gate level. Schedule a Time.|
Complete our quick verification survey at the booth and you will be entered into drawings for a Roku streaming media player and an Amazon Echo voice-controlled speaker!
To celebrate faster verification and design, enjoy a modern, high-speed espresso coffee from our DeLonghi Magnifica automatic coffee machine!
We will also be giving away power bank chargers, RI baseball caps, book light – laser pointer combos, and pens with a built-in stylus and light.
|For more information, please visit realintent.com/DAC/|
Fix X-pessimism in Netlists with Practical Techniques
| Lisa Piper|
Technical Marketing Manager
Most functional verification is done before the RTL is handed off for digital synthesis. Gate-level simulations take longer and are hard to debug, but still needed to verify some circuit behavior. Ideally, the output of the RTL simulation will match the output of gate-level netlist simulation after synthesis. But that is not typically the case. Besides the obvious things verified in your gate-level simulations, there are always unknown values (Xs). Some will not be seen in the RTL due to X-optimism, but there will be additional Xs in the gate-level simulations due to X-pessimism.
X-optimism in RTL and other generic issues around unknown states are discussed in more detail in the paper ‘X-Propagation Woes – A Condensed Primer‘. Some basic familiarity with the concept is assumed here.
This paper focuses on X-pessimism at the netlist level. It discusses some current techniques and their limitations, and then describes a more efficient X-pessimism strategy based on Real Intent’s Ascent XV.
What is X-pessimism?
X-pessimism occurs in gate-level designs when an X signal at the input of some digital logic causes the simulation output to be an unknown value, even though in real hardware the value will be deterministic (i.e., 1 or 0). X-pessimism makes it hard to get netlist simulations up and running quickly.
Figure 1 shows a simple example. When the values of in1 and in2 are both 0, the simulation value at the output is 0, as would happen in hardware. But when the ‘input’ value is an unknown X, and the values of in1 and in2 are both 1, the simulation value at the output is X in simulation but is 1 in real hardware. Specifically, we say it is 1-pessimistic because the output should have been a value of 1 (as the example suggests, ‘0-pessimistic’ is also possible).
Unlike Figure 1, the logic cone of the cloud in real designs is often very complex. The selected output can be driven by a logic expression and the input can also be a logic expression. In such cases, the output X value is sometimes a result of pessimism but at others simply the propagation of an X that was optimistic in RTL. One can be artificially corrected without harm, but the other could be a major bug. Refer to “X-Propagation Woes – A Condensed Primer”2 for more details.
Common ‘quick fixes’
Three techniques are frequently used to address X-pessimism:
- Eliminate all Xs.
- Perform artificial random initialization of uninitialized flops.
- Manual analysis.
All have major drawbacks. Let’s take a more detailed look at each.
The first step toward eliminating all Xs is to add a reset to all memory elements. This gets rid of the most common source of Xs: uninitialized flops. However, synchronous resets can lead to pessimism issues being introduced during synthesis. Also, there are other significant X-sources this does not address. These include explicit X-assigns for flagging illegal states, bus contention, and out-of-range references.
But the greater issue with eliminating all Xs is that the necessary resets eat into power, size, and routing budgets. Resettable flops are larger, consume more power, and require additional routing resources. The technique is practical only for smaller designs.
The second approach artificially randomizes the initialization of uninitialized memory elements at time 0. This helps in simulation but does not necessarily match real hardware. It also, again, does not address all X-sources. X-optimism bugs that were masked in RTL will probably be artificially masked again in the netlist simulation. Missing such a bug can lead to very expensive late-stage repair.
The third approach is to manually analyze the root cause of all X-differences between the outputs of the RTL and gate-level simulations, determine the correct values and time, and then force and release pessimistic nodes. This can be difficult.
A gate-level realization transforms RTL into something that is more complex, has a different structure, and has unfamiliar signal names. It takes a lot of time to chase down pessimistic Xs in netlist simulations, particularly where there is a mixture of Xs attributable to either optimism or pessimism – and you do not initially know which. The process can take months for large designs and even then it is easy to overlook bugs because of deadline pressures.
In summary, these established approaches do not address pessimism caused by Xs from all sources. They mask issues in the gate-level simulations due to X-optimism in RTL simulations. They cannot handle larger SoC designs.
If a node is determined to be 1- (or 0-) pessimistic, that means its real circuit value is 1 (or 0) but simulation will produce an X. A pessimistic simulation value can be corrected by forcing a 1 (or 0) on the node until the conditions for pessimism no longer hold – that is, the node represents the deterministic value real hardware would see. After forcing, the node must be immediately released.
But not all Xs should be arbitrarily forced to a known value, only those that result from pessimism.
Ascent XV-Netlist from Real Intent makes your gate-level simulation hardware-accurate by correcting pessimism as appropriate. It statically identifies potentially pessimistic nodes, then uses that information to create SimPortal files that augment the simulation to correct X-pessimism on-the-fly.
Undertaking static analysis before simulation significantly reduces the number of nodes that must be analyzed during simulation itself. Also, X-analysis during simulation can be reduced to a table look-up when the potentially pessimistic node has an X-value. The SimPortal files monitor potentially pessimistic nodes in the design as you go, independent of the testbench.
A bottom-up hierarchical static analysis can also be done at the block level. When all the blocks are integrated for full-chip simulation, this proves a very scalable approach. The SimPortal has been designed to minimize compile time and memory overhead. You can control the verbosity at simulation time, and choose to drop back to simple monitoring or even turn off both correction and monitoring at any point in time.
The Ascent XV X-pessimism flow and methodology has two main components and is shown graphically in Figure 2.
- Run static analysis to determine which data input values can cause monitored nodes to exhibit pessimism. Generate design-specific SimPortal data files.
- Run SimPortal simulation to find out which nodes experienced the input combinations that cause pessimism.
This methodology takes another complex issue out of fixing X-pessimism. In RTL, Xs can hide functional bugs due to X-optimism. These bugs will be brought to light in netlist gate simulations. Unfortunately because Xs also cause X-pessimism in netlist simulations, you then need the time and insights to determine whether a mismatch is due to X-optimism, X-pessimism, or something else.
Ascent XV-Netlist eliminates Xs caused by X-pessimism, removing the major source of simulation RTL and netlist simulation differences and thereby the need for manual analysis and filtering.
A full breakdown of Ascent XV’s features and advantages is shown in Figure 3.
Xs exist in all designs and it is difficult to prevent them occurring for practical reasons. Simulation results may differ because of Xs hidden in the RTL simulation by X-optimism, or present in gate-level simulation due to X-pessimism.
Pessimism can be fixed by overriding the simulator because you know that real hardware will always resolve to a deterministic value. The challenge is confirming that an X value is a result of X-pessimism and not simply X-propagation. Only then can you force it to the right value at the right point in time so that the simulation matches that for real hardware.
Ascent XV-Netlist Pessimism corrects X-pessimism on-the-fly so the simulation is hardware accurate. Ascent XV cuts the time required to get gate-level simulations started by an order of magnitude. Its ease-of-use and capacity, make it the only practical solution for large SOCs.
In Memory of Dr. Miles Copeland: Innovator and Mentor
| Graham Bell|
Vice President of Marketing at Real Intent
At Carleton University in Ottawa, Canada, Copeland was the former chair of the Department of Electronics and Professor Emeritus in the Faculty of Engineering and Design. He was an IEEE Fellow and was known for his passion for teaching and research innovation.
In addition to educating two and a half generations of electrical engineers, Copeland had established Carleton’s research capacity in the area of analog and radio frequency integrated circuit design, including the development of computing techniques to enable and reinforce research and learning.
The focus on computing techniques was how I came to work with Copeland.
As a recent graduate of the Department of Computer Science with a focus on computer hardware, I was hired by Dr. Copeland, as a research engineer, to port SPICE, a 14,000 line Fortran program, into a 16-bit microcomputer (Corvus Concept) that was based on the Motorola 68000 micro-processor. This allowed students to simulate their circuits before fabricating them in-house on the University’s 2-inch wafer line. Later on, I worked with Copeland on extending a mixed-analog digital simulator, SPLICE, to handle mixed sampled data circuits, specifically switched-capacitor filters. We published the research in an IEEE journal that led me to be hired to work on the PSPICE simulator in California. I owe my entire career in high-tech to Miles Copeland.
Copeland was actively involved in consultation and research collaboration with industry, notably at Nortel, Bell Northern Research and General Electric. His widely used research innovations include groundbreaking work that enabled the design of fully integrated radios. His research was also key to the design of modern telecommunications circuits that are used in today’s personal communications devices and wireless data communication
Over his distinguished teaching career, Copeland supervised nearly 50 masters and PhD students.
In recognition of his achievements, Copeland recently received the 2016 Institute of Electrical and Electronics Engineers (IEEE) Donald O. Pederson Award in Solid-State Circuits. For nearly a century, the IEEE has paid tribute to technical professionals whose exceptional achievements and outstanding efforts have made a lasting impact on technology and society. He was named a Fellow of the IEEE in 1989.
Copeland was presented with the prestigious award on February 1, 2016 at the International Solid-State Circuits Conference in San Francisco. While accepting the award, he reflected back on his time in the Faculty of Engineering and Design.
“This award recognizes Carleton’s leadership in engineering research and innovation,” noted Copeland. “I appreciate the acknowledgement of my hard work and that of Carleton graduate students, whose research helped Nortel establish itself early on as a dominant company in the telecommunications market.”
Dr. Copeland is missed by me and the many colleagues and friends in the Faculty of Engineering and Design at Carleton as well as hundreds of former students. A scholarship was recently established in Dr. Copeland’s name to support outstanding Electronics students. To make a contribution to the fund, please visit futurefunder.ca or contact Corrie Hobin, Assistant Director of Faculty Advancement, Engineering and Design at firstname.lastname@example.org for more information.
How SoC Design is Driving Constraints Management and Verification
| Graham Bell|
Vice President of Marketing at Real Intent
There were a number of announcements at DAC 2016 in Austin concerning SDC timing constraints verification and management. Real Intent announced the newest release of Meridian Constraints for sign-off of SoC designs. It features new and unique functional analysis, data-driven debug, and support for distributed design development.
In this blog, I want to cover the drivers for a new kind of Constraints verification tool.
Constraints Management today is clearly different from the pre-SOC and pre-IP eras. The design process is now truly distributed with much legacy and third-party IP in any new SOC design. This implies that the SDC creation process must go through the three steps of (a) aggregation from the component SDCs to an overall SoC-level SDC, (b) refinement of the SoC-level SDC, and (c) dis-aggregation of the SoC-level SDC into SDCs for the synthesis partitions. The key point here being that the synthesis-partition boundaries need not align with the logical boundaries of the component IPs.
In the pre-SOC and pre-IP era, SDC was created for the monolithic design just prior to synthesis followed by dis-aggregation (budgeting) for the synthesis partitions. It is a benefit that the component IP comes with the associated SDC, but it also means that the SDC management software must be able to digest the component SDCs and create a consistent monolithic SoC-level SDC, i.e. component SDC promotion to the SOC top-level along with SDC consistency checking becomes first-order requirements in an SDC management tool. This has been borne out in surveys we have done with designers, which reveal a 30% pain-point number for consistency checking.
SDC used to be needed first for synthesis followed by static timing analysis (STA), meaning that it was needed late in the design process. In the SoC era, sign-off activity occurs at the RTL level before synthesis partitions are decided. As an important example, RTL must be signed off for clock-domain crossing (CDC) checks before synthesis. Similarly, functional timing exceptions and Reset schemes must be signed-off in RTL before synthesis and STA. These sign-off items require a detailed clocking spec for the sign-off to be meaningful and robust. Not every single SDC detail required for synthesis and STA need to be present at this stage, but the SDC must be detailed enough for CDC sign-off to be reliable. In the SOC and IP-integration era, SDC is needed first for RTL sign-off followed by synthesis and then STA.
Missing and incorrect clock specs are important issues faced in the RTL sign-off process. Usually these gaps can be filled by an analysis of the design and providing the user with templates of SDC commands to be added to the existing constraints. This is borne out in our survey of designers in which the combination of constraints checking, constraints creation and exception verification stands out as a major overhead.
Depending on design methodology, it is true that many exceptions may be “timing intent”, i.e. static configuration registers, resets, etc. These are not the types of exceptions that can result in silicon failures. The 20-30% of structural failures cost 100% of the time and money for a re-spin, and it’s important to have a methodology that can validate them completely. This requires not only a structural analysis of hardware control structures for multi-cycle paths, but also a complementary formal methodology to find any corner cases. In addition, the ability to configure your exception validation via assertions is crucial to having a complete understanding of your design operation and assumptions before taping out.
If we look at sign-off from the perspective of CDC verification, some tool vendors suggest that the CDC setup process is all about getting clean SDC at RTL level. Getting clock information right is a first step in CDC methodology but it’s just the first step. For a CDC tool to be noise free and waiver free, it should be configurable so it can understand and adapt to various CDC design styles/methodologies used by different design teams across the industry. Also SDC itself is limited because its written for timing intent only, so SDC has no information about what resets signals are in the design.
Meridian Constraints from Real Intent meets the needs of design teams to create, manage, and verify all of their SDC timing constraints. It also ensures that constraints completely cover the design, correctly match the functional and timing goals, and are consistent between different blocks and levels in the design. Having correct and complete constraints and associated clock definitions ensures timing goals are met. Leveraging functional analysis capability with industry-leading formal analysis technology in Meridian Constraints gives users maximum confidence in the correctness of their exceptions, minimizing the risk of a re-spin due to bad exceptions that cause incorrect circuit operation.
This article was based on contributions by Pranav Ashar, CTO, Vikas Sachdeva, senior technical marketing manager, and Daryl Kowalski, senior manager of product engineering at Real Intent.
DAC Preview: 6 Tech. Presentations, Panel on Verification Cost, and the BEST Parties!
| Graham Bell|
Vice President of Marketing at Real Intent
Real Intent is bringing its advanced Ascent and Meridian technology, EDA expertise and espresso energy to the 53rd Design Automation Conference (DAC) in Austin, Texas, June 5-9, 2016. Before I mention the BEST DAC parties, Real Intent invites attendees to Booth #527 to:
- Learn the latest information about Real Intent’s Ascent family of tools for the fastest static RTL verification prior to synthesis and simulation, and its Meridian tools that enable CDC and SDC sign-off at the RTL and gate-level.
- View technical presentations to get up to speed on Real Intent’s latest advancements, proven on giga-gate SoC and FPGA designs. Click here to make an appointment for one of our private suite presentations:
- How to Accelerate Your RTL Sign-off
- Ascent Lint with New Visualization and VHDL 2008
- Meridian CDC with New Analysis and Data-driven Flow
- Ascent XV with Advanced Gate-level Pessimism Analysis
- Case Studies in Physical CDC Analysis for Gate-Level Sign-off
- New Next-Generation Constraints Exception Verification
- Complete a quick verification survey to be entered into drawings for a cool Roku 4 streaming player and an Amazon Echo wireless speaker and voice commander.
- Espresso Yourself and enjoy a high-speed coffee from our DeLonghi Magnifica super-automatic coffee machine, to celebrate faster verification and design.
- Visit Real Intent and OpenText (Booth #638), Real Intent’s “Espresso Yourself” partner at DAC; get a ticket stamped by both companies to enter drawings to win $100 Amazon Gift Cards.
- Receive a rose as a sweet thank-you gift.
Real Intent also invites attendees to view What is the Real Cost of Verification — a stimulating panel on Thursday, June 9, from 3:30-4:30 p.m. in room 18AB. Moderated by Kelly Larson of Paradigm Works, panelists Harry Foster of Mentor Graphics Corp., Pranav Ashar of Real Intent, Inc., Raviv Gal of IBM Research, and Subhasish Mitra of Stanford University will discuss what design cost really includes. They also will explore how to measure and improve verification coverage, reduce rework, and improve the chances of first-time silicon success.
BEST DAC PARTIES
Kick-off your DAC with the Welcome Reception, 5:30pm – 7:00pm, 4th floor foyer of the convention center. Just before, from 5;00pm – 5:30pm is the Gary Smith EDA at the ESD Alliance Kickoff in Ballroom D.
HOT Party, Speakeasy, 412 Congress Ave., 7:30 pm to 11:30 pm
Join Heart of Technology and their sponsors at the swankiest party at DAC. They’ll be pouring the giggle water and serving the eats, Al Capone style. Entertainment will be provided by Killer Tofu, the 1990s band playing Green Day, TLC, Grunge and other music you crave. Once again, we are supporting CASA of Travis County with this fundraiser. It’s going to be the bees knees, man! So get your rags together and join us on June 6 at the Speakeasy, voted Austin’s “best swanky” and “best place to party.” Free to get-in, donations accepted. Tickets here: HOT Party at DAC 2016
The Denali Party By Cadence, Tuesday, 8:00pm to 12:30am, Maggie Mae’s, 323 E 6th Street. You need to pre-register (do it now) and you must pick up your wristband at the Cadence booth #107 before noon on Tuesday, or your reservation will be given to another guest.
Stars of IP 2016, 8:00 pm to 1:00 am, Revival Public House, 340 E 2nd Street
(right across the street from the Austin Convention Center), ticket required.
This is a private party organized by IPextreme and their IP partners and friends. Visit one of the co-hosts below on the DAC Exhibit Floor to inquire about spare tickets.
Mon., Tues., Wed., Thu.: Don’t forget the daily receptions, 6:00pm to 7:00pm, (5:30pm on Thu.) in the Trinity Street Foyer of the convention center.
See you at the show!
The Switch from Atrenta to Real Intent for CDC, Lint, and X-prop
| Graham Bell|
Vice President of Marketing at Real Intent
John Cooley’s Deepchip.com web-site likes to publish end-user experience with various EDA tools. On May 6, he published a posting on why a designer switched from Atrenta SpyGlass to Real Intent for CDC, Lint, and X-propagation analysis. His report details the reasons for converting to our best-in-class tool suite.
Here is the first part of the posting:
We had been using SpyGlass from Atrenta, and it worked OK for us, but we
were told by our local Real Intent sales guy that “there would be fewer
iterations for Lint, easier setup for CDC, lower-noise reporting, and
faster runtimes” — if only we evaled his tools.
REAL INTENT MERIDIAN CDC VS. ATRENTA SPYGLASS CDC
I spent one work week (5 days) evaluating Meridian CDC. We used different
designs to evaluate this tool. The first was 850K gate design that had
3 asynchronous clock domains. For the analysis setup, Meridian CDC
automatically detected all the clock/reset candidates correctly at block-
level as well as the top-level. No additions were needed for the setup
file, while our Spyglass run did require manual editing of the setup.
The Meridian runtime for this block was ~5 minutes.
The second design was 4 million gates and had 5 asynchronous clock domains.
Again the automatic clock/reset detection worked as expected. The runtime
was ~15 minutes.
Read the rest of the report on CDC, lint and X-propagation here.
Have you switched EDA tools recently? How was that experience?
May 17 Event: More than Moore – Enabling the Power of System Scaling
| Graham Bell|
Vice President of Marketing at Real Intent
More than Moore – Enabling the Power of System Scaling:
|Join the ESD Alliance on the evening of May 17th at 6PM when we will be hosting an open dialogue about system scaling solutions and what it will take to propel them into the mainstream for semiconductor design and manufacturing. Although various system scaling technologies (such as interposer-based designs, using die-level IP blocks, like HBM) are already in use today, they have not yet crossed into the mainstream.
System scaling offers an excellent alternative path to pursuing Moore’s Law by moving the integration focus from the transistor to the integration of several heterogeneous pre-fabricated and proven devices, in the form of die-level IP, into an advanced IC package. Although new sub- 10nm process technologies continue to drive Moore’s Law, development cost and times at these advanced nodes are beyond the reach of much of the mainstream market.
It will take collaboration and cooperation between modeling, design, analysis/verification, manufacturing and test in order to unlock the potential of these new integration solutions. The objective for the meeting is to have an open discussion to identify the highest priority issues that should be jointly worked on to streamline the path to widespread adoption. The ESD Alliance is in the process of forming a working group representing both manufacturing and design to work on practical solutions and is seeking community input on direction and priorities.
This is an open event and we encourage anyone who is involved with or interested in system scaling from either the design or manufacturing perspective to attend. Please join us at 6 pm for networking, food and beverages prior to the open discussion forum, starting at 6:30.
7 Design Faults Leading to Clock and Data Glitches
| Graham Bell|
Vice President of Marketing at Real Intent
It is very important to make digital designs free of any clock or data glitches to ensure correct functioning. There are many cases where such issues have caused functional failure, or increased design time through incurring extra debug effort. Hence, it is very important for a designer to take care of such issues at the earliest stages of design once flagged by a tool or gate-level synthesis.
Here is his introduction followed by an iframe of the article from EDN magazine.
With the increasing complexity of SoCs, multiple and independent clocks are essential in the design. The design specifications require system level muxing of some of these clocks before they are sent to actual IP. Also, to save power, clock gating cells are inserted in clock paths. While implementing these muxing and gating cells, a designer tends to make mistakes that can lead to glitches. A glitch on a clock signal exposes a chip (or a section of a chip) to asynchronous behavior. A glitch-prone clock signal driving a flip-flop, memory, or latch may result in incorrect, unstable data. This paper discusses structural faults that can lead to glitches in clocks. Also, some bad design practices that lead to glitches in data are discussed. Read the rest of 7 Design Faults Leading to Clock and Data Glitches
DVClub Silicon Valley: “Using UVM Virtual Sequencers & Virtual Sequences”, Wed. Apr. 27
| Graham Bell|
Vice President of Marketing at Real Intent
Please join Silicon Valley verification and design engineers on April 27, 2016 at Dave and Buster’s in Milpitas for a catered lunch, networking, and presentation by Cliff Cummings. This is a no charge event.
11:30am: Doors Open / Networking
12:00pm: Lunch / Presentation
“Using UVM Virtual Sequencers & Virtual Sequences”
What are virtual sequencers and virtualssequences and when should they be used? Tests that require coordinated generation of stimulus using multiple driving agents benefit from using virtual sequences. This presentation will clarify important concepts and usage techniques related to virtual sequencers and virtual sequences that are not well documented in existing UVM reference materials. This presentation will also detail the m_sequencer and p_sequencer handles and the macros and methods that are used with these handles. The objective of this presentation is to simplify the understanding of virtual sequencers, virtual sequences and how they work.
Cliff Cummings is President of Sunburst Design, Inc., a company that specializes in world-class SystemVerilog, Synthesis and UVM Verification training.Cliff has presented hundreds of SystemVerilog seminars and training classes and has been a featured speaker at multiple world-wide SystemVerilog and Assertion Based Verification seminars. Cliff has been an active participant on every IEEE Verilog and SystemVerilog committee, and has presented more than 50 papers on Verilog & SystemVerilog related design, synthesis, and OVM/UVM verification techniques, including more than 20 that were voted “Best Paper.” Cliff holds a BSEE from Brigham Young University and an MSEE from Oregon State University.