P2415 – New IEEE Power Standard for Unified Hardware Abstraction
Graham Bell Vice President of Marketing at Real Intent
The IEEE announced in September that is was launching working a on a new power standard called P2415. This blog gives the background for this new effort.
The current low power design and verification standard (IEEE 1801-2013 and IEEE P1801) is focused on the voltage distribution structure in design at Register Transfer Level (RTL) description and below. It has minimal abstraction for time (having only an interval function for modeling clock frequency), but depends on other hardware oriented standards to abstract events, scenarios, clock trees, etc. which are required for energy proportional design, verification, modeling and management of electronic systems. The necessary abstractions of hardware, as well as layers and interfaces in software are not yet defined by any existing standards.
The energy design and management flow for electronic devices is disconnected among different stages of the design process and lacks the abstractions, formats, interfaces, and automated methodologies long established and standardized in functional design and verification of hardware and software for electronic systems. The main disconnects on energy issues are at the handover points between various design teams:
From VLSI designers and IP providers to system integrators and power designers at the RTL level
From system integrators to firmware developers at the core system software level
From device developers and firmware developers to OS integrators at the OS API level
From device developers and OS integrators to the application programmers at the application software level
The new P2415 standard has the goal to remove the above disconnects and lead to a well-connected energy oriented design flow enabling energy proportionality as the main design principle. It addresses energy proportionality through tight interplay between energy-oriented hardware and energy-aware software. It provides new design, verification, modeling, management and testing abstractions and formats for hardware, software and systems to model energy proportionality, and enables the design methodology that naturally follows the top-down approach – from the system and software down to the hardware.
The new standard defines the syntax and semantics for energy oriented description of hardware, software and power management for electronic systems. It enables specifying, modeling, verifying, designing, managing, testing and measuring the energy features of the device, covering both the pre- and post-silicon design flow.
On the hardware side the description covers enumeration of semiconductor intellectual property components (System on Chip, board, device), memory map, bus structure, interrupt logic, clock and reset tree, operating states and points, state transitions, energy and power attributes. On the software side the description covers software activities and events, scenarios, external influences (including user input) and operational constraints; and on the power management side the description covers activity dependent energy control.
The new standard, once completed and approved, will be intended to be compatible with the current IEEE 1801™-2013 (UPF) standard to support an integrated design flow. Additionally, the new standard would complement functional models in standard hardware description languages IEEE 1076™ (VHDL), IEEE 1364™ (Verilog), IEEE 1800™ (SystemVerilog), and IEEE 1666™ (SystemC), by providing an abstraction of the design hierarchy and an abstraction of the design behavior with regard to power and energy usage.
“IEEE P2415 will provide the higher level of energy abstraction for the system-on-chip and the whole device and, therefore, will enable earlier (more abstract) modeling of power states using the IEEE 1801-2013 (UPF) standard,” said Dr. Vojin Zivojnovic, chair of the IEEE P2415 working group and CEO of Aggios, Inc. “Many software engineers and system architects will find this effort well-aligned with their need to communicate their low-power and energy requirements with the hardware engineers in an aligned fashion for holistic, quantifiable and reusable energy optimizations. I welcome them to participate in this industry-wide effort.”
To participate in the new working group you can contact Dr. Zivojnovic at the following email: vojin.zivojnovic [at] aggios.com
This article was originally published on TechDesignForums and is reproduced here by permission.
It’s tempting to see lint in the simplest terms: ‘I run these tools to check that my RTL code is good. The tool checks my code against accumulated knowledge, best practices and other fundamental metrics. Then I move on to more detailed analysis.’
It’s an inherent advantage of automation that it allows us to see and define processes in such a straightforward way. It offers control over the complexity of the design flow. We divide and conquer. We know what we are doing.
Yet linting has evolved and continues to do so. It covers more than just code checking. We begun with verifying the ‘how’ of the RTL but we have moved on into the ‘what’ and ‘why’. We use linting today to identify and confirm the intent of the design.
A lint tool, like our own Ascent Lint, is today one of the components of early stage functional verification rather than a precursor to it, as was once the case.
At Real Intent, we have developed this three-stage process for verifying RTL:
Initial RTL: Requirements may still be evolving. Design checks here ensure that regressions and builds failures are caught early.
Mature RTL: Our concerns now revolve around such issues as modeling and its costs, simulation-synthesis mismatches, FSM complexity and so on. The focus is on higher order aspects of freeze-ready RTL that might impact design quality. These ‘mature RTL’ checks ensure necessary conditions for downstream interoperability.
Handoff RTL: By this late stage, checks are geared towards compliance with industry standards or internal conventions to allow easy integration and reuse.
Applying those three stages to lint tools gives us the following diagrammatic representation of how they can be applied.
Linting plays an increasing role in this process because better tools now use policy files that are both appropriate and adaptable at each of the three stages. They still detect coding errors but also monitor that further satisfaction of design intent. We can use linting to begin the deep semantic analysis of designs now needed to manage their increasing complexity.
Lint as a semantic analysis platform for verification
Semantic analysis is an approach that we might more immediately associate with tools run after linting to analyze, say, clock domain crossings or troublesome X states. If we consider linting as an example of early stage functional verification rather than simple code checking, it becomes natural for it to also undertake such an analysis, addressing issues with the relationships between different elements as soon as possible.
The results from a linter therefore tell us a great deal about the state of the design. The tool should catch problems that require immediate debug but also provide data that help us plan and refine the verification plan going forward.
Can some issues be seen as settled, needing no further investigation? Do others require examination in particular detail?
A good linter helps us to allocate resources. This is in addition to features that look toward debug. Ascent Lint, for example, has Emacs editor integration to make the find-and-fix loop faster and easier.
These are not the linters of the past. But even they may be only the beginning. For example, as intelligent testbenches evolve, they are also incorporating more capability for semantic analysis. The opportunity here alone for greater integration and efficiency is self-evident.
Lint may be an established, even mature concept but continues to evolve in exciting directions and how it fits in your flow today should not be taken for granted.
Parallelism in EDA Software – Blessing or a Curse?
Graham Bell Vice President of Marketing at Real Intent
To satisfy demands for lower-power and higher performance, the use of multiple CPU cores is a norm in SoC design. The interaction of multiple cores and the surrounding semiconductor IP, presents new challenges to verification. But what about EDA tool providers? How can the use of multple CPUs improve performance and throughput in their tools? What software caveats do they need to be aware to support processing by parallel CPUs? Pranav Ashar, CTO at Real Intent gives his perspective below.
EDA tools must be exploit parallelism to keep up with SoC complexity, or we will be attempting to designing next-generation chips on what effectively will be antique hardware.
A couple of factors have combined to reduce the pace at which parallelism has been adopted in EDA tools. It is common to overlook the latency impact when designing parallel programs that communicate with physical memory. Cache-coherency and memory access latency are often encountered examples that lowers the processing throughput of a tool on a multi-core processor. Fine-grain multi-threading in EDA tools quickly triggers some of these latency bottlenecks – for the typical SoC benchmark, these limits are reached rather rapidly.
It is also challenging to write bug-free multi-threaded programs. Revamping a large existing code base to become multi-threading friendly is a nontrivial re-engineering undertaking. Below, we present a list of Do’s and Don’ts for coding multi-threaded programs courtesy of Guy Maor, an experienced EDA developer.
Multi-process parallelism has become a viable alternative to multi-threading as a result of much lower overheads compared to previous generations of hardware. Also, compared to the multi-threading approach, process-based parallelism triggers fewer latency issues and is easier to ensure correct operation, and has excellent API software libraries available.
There is plenty of low-hanging parallelism available in EDA tools in their front-ends and analysis engines that, with a careful program architecture and data-flow to minimize inter-process copying overheads, can be harnessed with multi-process parallelism. This can be a way to introduce parallelism into an EDA tool in an evolutionary manner.
Even with the known limitations of current multicore architectures, EDA companies must push ahead with parallelizing their software. An 8x speed up on a 32-core processor is better than no speed up at all. It is also one way of determining what the limits are, and where system and software rearchitecting is needed.
Do’s and Don’ts for Developers of Parallel Software by Guy Maor
Remember Amdahl’s Law
Your core algorithm will scale but the full flow often gives much less e.g. 2-3X improvement
Improving your core algorithm makes the full-flow scaling worse and harder to achieve
Design for Deployed Hardware
Typical server farms have 2-4 sockets, 4-8 cores per socket, 4-8 GB of memory per CPU core.
Most EDA tools are memory limited, so cores are free
Don’t waste your time on GPUs or other esoteric hardware. It makes adoption harder and will not deliver the ROI you are looking for.
The tool must produce the same result irrespective of the number of cores as customers expect it and becomes impossible to debug
Design for Input/Output
Input/Output is the bottleneck
Disks have good bandwidth but high-latency that must be managed
Design for Memory
Use a multi-threaded memory allocator in your code (malloc)
Avoid transfer of ownership in your code
Minimize shared memory and global variables
Always be Profiling Your Code’s Performance
Identify mutex bottlenecks (locking memory for I/O)
Profile user experience of the tool in the field
Use a sample-based profiler because they have a low-overhead.
What has been your experience with parallelism in design and tool development? Did you get the speed and throughput improvement you were shooting for?
Graham Bell Vice President of Marketing at Real Intent
Its a fact of life that semiconductor design is a world-wide activity, and that EDA companies are helping customers in a 24 hour day. How international is this world? According to the latest statistics from the EDA Consortium, over 50% of the business activity is outside North America. The total of EDA, semiconductor IP and design services revenue was 6.9 billion dollars in 2013. Comparing this to a world population of 7.1 billion means roughly one dollar per person was spent on the wide world of design.
While Real Intent is not a large company in the world of EDA, we do have representation for our verification products through-out the world and have just added two new distributors in Asia.
In India, we added a second distributor, Claytronic Solutions. This move extends Real Intent’s customer care efforts worldwide and addresses growing demand among design teams throughout India for local expertise and support of Real Intent’s advanced verification solutions.
Incorporated in 2010, Bangalore-based Claytronics provides specialized services and expertise at each stage of a product’s life cycle; it accelerates and simplifies the journey from concept to market with one-stop shopping for solutions and products in consumer electronics, multimedia, automotive and infotainment, and defense and aerospace. Claysol’s management team has deep design expertise and holds patents in multi-core parallel processing, multi-core architecture and video processing. In our view Claysol offers the uncompromising level of service and support we were looking for to meet the surging interesting the Indian market.
Umesh Tallam, Engineering Director of Claytronics, is looking forward to the new collaboration since “partnering with leading international vendors like Real Intent provides our customers unparalleled tools to help them build globally competitive products quickly and cost-effectively.’
The move strengthens Real Intent’s local sales and support for handling Taiwan’s fast-growing interest in Real Intent’s solutions for early functional verification and advanced sign-off verification. It also complements Real Intent’s existing sales and support teams in the rest of Asia.
Kaviaz, which means “best friend,” was established in 2008 to provide the best possible service and support for EDA customers in Taiwan. Its broad expertise spans logic design and verification tools, analog/mixed-signal tools, physical implementation and analysis tools, mask tools and IP distribution.
We picked Kaviaz since it is renowned for its long-standing technical expertise in the EDA arena, and for its uncompromising dedication to addressing customer needs. We think this synergistic partnership brings proven ways to accelerate design sign-off to electronic engineering teams throughout Taiwan
Timing Huang, president of Kaviaz Technology, has told me he is always seeking out leading-edge verification solutions for innovative companies in the Taiwan market looking for efficiency gains. He thinks Real Intent’s Ascent and Meridian products will boost the productivity of his clients.
Real Intent is looking to expand further into Asia in support of our growing customer list. Stay tuned for further announcements.
Graham Bell Vice President of Marketing at Real Intent
I still get the daily newspaper delivered to my house, the San Jose Mercury News. I came across the obituary for John Haslet Hall, one of the leading innovators at the birth of CMOS technology in Silicon Valley. I had not heard of Hall, and thought that you might also want to learn of his many wide-ranging contributions to the world of semiconductors.
John Haslet Hall, son of the late William McLaurine Hall, Jr and Mary Helen (Ent) Hall, was born July 11, 1932 and died October 30, 2014.
Hall was an early and prolific Silicon Valley inventor. In a career that spanned over 60 years, Hall developed technology included in over 20 fundamental patents, including pioneering work in low-power CMOS integrated circuit technology. A 1992 San Francisco Chronicle article referred to Hall as, “one of Silicon Valley’s unsung innovators.”
Hall served in the U.S. Navy in the late 1950s, working with aircraft electronics development and testing, often riding in planes that were pulling target drones to collect data. He graduated from the University of Cincinnati in 1961 and sought to apply his chemical engineering education in the nascent semiconductor industry.
In 1962, Hall met semiconductor pioneer Dr. Jean Hoerni, a cofounder of Fairchild and inventor of the planar process, the basis of today’s electronics industry. Hoerni and Hall worked on several consulting projects together, which led to Hoerni asking Hall to work for him at Union Carbide. Hall’s work there included the development of the first on-board aircraft computer made entirely of integrated circuits (ICs), used for the SR-71 Blackbird.
Hall worked as Union Carbide’s director of IC Development from 1962 to 1967, and his years there included innovations that would lead the semiconductor industry. These include the first application of thin-film technology; the first dual transistor on a single chip; and the invention of dielectric isolation technology. The Union Carbide semiconductor plant Hall built in Mountain View later became Intel’s first production facility.
In 1968, Hoerni asked Hall to join him in the formation of a new company, Intersil. As co-founder of Intersil, Hall headed R&D and achieved a breakthrough in coating silicon oxide gates with phosphorous glass resulting in the first practical metal oxide semiconductor (MOS) processes. Hall’s Intersil team also develop the first N-Channel memory chip at a time when most companies overlooked its potential.
Hall’s work in thin film resistors and CMOS technology formed the basis of Intersil’s electronic watch development for Seiko, which was chosen over a competing bid from RCA. Hall’s watch was the first successful quartz crystal watch, running on a one-volt battery that would last over a year.
Following the sale of Intersil in 1968, Hall declined Hoerni’s offer to join him in a new venture and opted to go out on his own with the backing of Seiko. Hall went to Japan to be the principal architect of Seiko’s – and Japan’s — first CMOS fabrication facility in 1970.
In 1971, Hall founded Micro Power Systems and for the next 15 years produced a string of commercial and technical successes. In one example, Hall competed with Motorola and Texas Instruments in a bid to Medtronics to create a computerized heart pacemaker. Hall’s design allowed the pacemaker to operate for 10 years without a battery replacement and enabled doctors to change its settings via remote control rather than invasive surgery.
In 1986, after a highly publicized technology transfer dispute with Seiko’s new management, still a key investor at his company at the time, Hall was forced to leave Micro Power Systems. He initiated a lawsuit against Seiko that was settled out of court in 1990. Hall in 1987 founded Linear Integrated Systems, Inc. and continued to develop new IC and specialized discrete device technology. At the time of Hall’s death, he was continuing to lead the company as chairman of the board and chief executive officer and was conducting research into further noise reduction in junction field effect transistors.
In a departure from his semiconductor endeavors, Hall in 1992 founded Integrated Wave Technologies, Inc., (IWT) a speech recognition company that employed former Soviet scientists and engineers. As a sister company to Linear Systems, IWT developed body worn speech recognition devices for DARPA, the Air Force, the Navy and the Department of Justice. These devices were highly successful in Iraq and Afghanistan operations, and IWT’s work was recognized as a significant accomplishment in the book DARPA: 50 Years of Bridging the Gap.
Hall was preceded in death by his parents, his brother William, sister Jean Anderson and son Richard Hall. He is survived by his children John Michael Hall (Sondra), Jennifer Hall, Jasmine Hall, Mary Helen Hall, and five grandchildren; Michael, William, Ozzalyn, Isabella and Sloan. Services to be held Monday, November 10, 2014 10:00 a.m. at the Calvary Cemetery, 2650 Madden Avenue, San Jose, 95116. Reception to follow at 12:00 p.m. Mariani’s, 2500 El Camino Real, Santa Clara, CA 95051
Is Platform-on-Chip The Next Frontier For IC Integration?
Srinivas Vaidyanathan Staff Technical Engineer
I was musing the other day about the completeness of SoCs – they include a mix of embedded processors for programmable functionality, hardware engines that accelerate specific features such as graphics, and multiple interfaces for memory, buses, and peripherals. And this remarkably complete solution is delivered on a single die. We have the perfect building block for creating systems with high-value and low-cost. But, even with Moore’s law allowing us to build more complex silicon, is new feature integration a scalable future for SoCs?
My conclusion is that we are approaching a steady state. From what I see, SoC design is still a custom solution in many ways, tailored to fit a generation of parts that meet some specific requirements. While complete in itself, the features cast in silicon offer only a coarse control of functionality. This leaves the end-user having to provide additional software and hardware to fill in any feature gaps at additional cost and time spent. While the intended and configured functions of the SoC might been implemented, any feature extensions may have compromises in performance.
When choosing between speed and configurability, designers make the choice of using either software running on a processor, or custom dedicated hardware. Software is ever forgiving, allowing multiple iterations towards the desired goal. On the other hand, hardware’s rigidity offers quick and reliable execution. Ideally, any desired feature enhancement would sit somewhere in this speed-configurability spectrum. Including this option in the SoC arsenal would allow for the perfect platform to unlock additional potential from hardware.
If we borrow an idea from the world of FPGAs, SoCs can gain significant versatility in providing the reconfigurability of software in dedicated hardware. Traditionally, FPGAs are looked at for hardware designs that are continually evolving; giving design teams the flexibility of keeping pace with change without the capital expenditure necessary for fixed silicon. For SoC customers, however, the constraints on area and power are just as critical as cost. Hence, a viable solution could be to include Programmable Gate Arrays (PGAs) in SoCs. In doing so, the choice of enhancing hardware can be weighed in context to other requirements. Importantly, this pushes out the hardware-software partitioning decision to much later in the product cycle, than currently available to developers today.
While the hybrid concept of mixing fixed silicon with FPGAs has been explored before, the key difference today is the growing software developer community that has been built around SoCs. To put this in context, consider the organization of the Andriod Software Stack on a SoC, using the example of the Ti-OMAP in the figure below. You can see there are fixed associations between the underlying hardware and the upper layers of software abstraction. However, introducing a PGA in hardware adds a completely new dimension to the software stack. Software libraries that were previously routed through the processor, for lack of a dedicated hardware, can now be offloaded to custom hardware created on-the-fly. Even libraries that have dedicated hardware accelerators, like graphics, can be augmented to cater to customized product requirements. By using some imagination, we can envision self-evolving hardware, morphing to suit the dynamic demands that applications place.
Obviously, there is more work required in the software stack to ensure that the generated hardware does not violate system parameters. But with that said, the capabilities in an architecture that bundles SoC and PGAs on a single die has the potential to be the ideal platform for endless product possibilities. I call this new innovation Platform-on-Chip (PoC).
While an interesting idea, is there a market for PoC? Consider Google’s Project Ara, a modular smart phone that is designed to swap out modules to suit the end-users’ usage needs. Among its many goals, this device is aimed at reducing e-waste by allowing the user to “upgrade individual modules as innovations emerge” . For a SoC, the possibilities of adding customized features, however, are restricted to the breadth of options the underlying SoC provides. With a PoC and its PGA component, emerging innovations are allowed more room to grow, and further extend the platform’s lifetime. Extrapolating the idea even further to the impending growth of the Internet of Things (IoT), there would be new ways for developers to re-purpose silicon in meeting with non-standard requirements at faster hardware speeds. A parallel topic of application could also be security. In an era where personal information is increasingly finding its way onto Internet enabled devices, real time reconfigurable hardware can offer stronger means of achieving identity protection.
If we have reached the end of innovation for SoC, do you think PoC could be the answer?
DVClub Shanghai: Making Verification Debug More Efficient
Ramesh Dewangan Vice President of Application Engineering at Real Intent
DVClub Shanghai took place on Sept. 26, 2014 with presentations by Real Intent, Solvertec, Mentor Graphics, Cadence, Synopsys and ARM. The theme of the meeting was “Making Verification Debug More Efficient.” Before I talk about two of the presentations that were recorded, here is some quick background on DVClub Shanghai which started at the end of 2013.
The principle goal of DVClub is to have fun while helping build the verification community through quarterly educational and networking events. The DVClub events are targeted to the semiconductor industry in China, with a focus on design verification. Membership is free and is open to all non-service provider semiconductor professionals. Most members work in verification, but there are also plenty of entrepreneurs, students, managers, investors, and even design engineers who attend. There are at least 4 events every year: March, June, September and December.
Mike Bartley opened the event with a talk that was titled “Improving Debug – Our biggest Challenge?” If you follow the link you can see the recording of his presentation, where he talks about the 6 things that we need for improved debug.
Even with high degree of design reuse, verification continues to be the long pole in design development. This has created a huge stress in current functional verification methodologies, which rely primarily on dynamic verification. Design complexity has made debug cycle times unpredictable and longer.
Static verification is a perfect complement to the dominantly dynamic verification in use today. Not only is static verification exhaustive, it needs minimal setup and offers faster debug cycles. Both structural and formal techniques have made dramatic advances in the recent years by analyzing the designer’s intent. Structural static verification has expanded its effectiveness to several critical application domains. And formal techniques have progressed from an expert-user model to a mainstream-user model.
The static verification techniques have been successfully used in targeted problem domains like clock domain crossing, reset optimization, X-optimism/pessimism, FSM integrity and so on. My presentation provides specific design examples and how the static techniques solves them more efficiently.
Not every verification problem is a nail that you need big hammer for. Simulation is too expensive and time consuming for a majority of verification problems. Why not, ease the pain by using faster, targeted, and exhaustive static verification techniques to shorten your verification debug cycle?
ARM TechCon Video: Beer, New Meridian CDC, and Arnold Schwarzenegger ?!
Graham Bell Vice President of Marketing at Real Intent
At ARM Tech Con 2014, I discussed beer, the new release of our Real Intent clock-domain crossing software Meridian CDC, and a new spokesperson for our company, with Sean O’Kane of ChipEstimate.TV. Enjoy!