Real Intent Product Families
Real Intent offers two product families – Ascent for early functional verification before synthesis; and Meridian for advanced sign-off verification not possible with simulation or static timing analysis.
Ascent for Early Functional Verification
Ascent Lint is the industry’s fastest and lowest-noise RTL lint solution. It includes smart rules that perform syntax and semantic checks for today’s complex System-on-Chip (SoC) designs. Ascent Lint is unique in the industry in terms of delivering high capacity, comprehensiveness and ease of debug.
Ascent AutoFormal is an early functional verification tool that automatically finds elusive bugs in RTL. It performs comprehensive verification using automatic check formulation followed by deep-sequential formal analysis. Ascent Autoformal can improve verification efficiency substantially and detect up to 50% of design functional errors prior to testbench development and simulation. It is the only automatic formal tool with root cause analysis, drastically reducing the debug time and the number of iterations necessary to get to functional closure.
Ascent X-Verification System (XV) addresses X-propagation issues, including isolating potential X-optimism at RTL and the correction of unnecessary X’s (X-pessimism) in Netlist. Eliminating X-optimism at RTL makes the transition to FPGA-modeling much faster by making the RTL simulations hardware accurate. Ascent XV also makes the transition to gate level simulation faster by identifying and correcting pessimism in gate level simulations. Ascent XV drives cost down by avoiding the monotonous, error-prone debug at the netlist level or within an FPGA model.
Meridian for Advanced Sign-off Verification
Meridian CDC is the fastest, highest capacity and most precise CDC solution in the market. It performs comprehensive structural and functional analysis to ensure that signals crossing asynchronous clock domains on ASIC, or FPGA devices are received reliably. With giga-gate capacity, Meridian CDC is the only solution that enables all aspects of CDC sign-off.
Meridian Physical CDC is the only solution available which does complete glitch checking and netlist sign-off. It performs comprehensive structural and functional analysis to ensure that signals crossing asynchronous clock domains on ASIC, or FPGA devices are received reliably at the netlist gate-level. Complementing Real Intent’s Meridian CDC solution that provides comprehensive analysis for RTL sign-off, Meridian Physical CDC provides enhanced netlist sign-off for 500M+ gate designs.
Meridian Constraints is the best in class, comprehensive constraint management solution in the market. It offers high performance constraint validation, template generation, coverage analysis, equivalence checking and timing exception verification capabilities designed to provide users with ultimate confidence in the timing constraints employed across all phases of the implementation flow.
iDebug is the state-of-the-art debugging environment for its suite of products for the verification of digital designs. iDebug provides an intuitive debugging experience that is universal across all Real Intent tools. It employs a database for the intelligent hierarchical analysis of design intent. It includes an integrated visualization capability, iVision, that provides design source browser, schematic and waveform visualization. The intent analyses of iDebug distinguish the root cause of issues, and minimize iterations and debug time, enabling powerful sign-off mechanisms.