Real Intent Product Families
Real Intent offers three product families– Ascent for early functional verification before synthesis, Meridian for advanced sign-off verification not possible with simulation or static timing analysis, and Verix for true multimode sign-off verification unlike anything else in the market.

Real Intent Products Info

Ascent for Early Functional Verification
Ascent Lint is the industry’s fastest and lowest-noise RTL lint solution. It includes smart rules that perform syntax and semantic checks for today’s complex System-on-Chip (SoC) designs. Ascent Lint is unique in the industry in terms of delivering high capacity, comprehensiveness and ease of debug.
Ascent AutoFormal builds on Ascent Lint to find elusive bugs in RTL. It performs comprehensive verification using automatic check formulation followed by deep-sequential formal analysis. Ascent Autoformal can improve verification efficiency substantially and detect up to 50% of design functional errors prior to testbench development and simulation. It is the only automatic formal tool with root cause analysis, drastically reducing the debug time and the number of iterations necessary to get to functional closure.
Ascent X-Verification System (XV) addresses X-propagation issues, including reset optimization, isolating potential X-optimism RTL and the correction of unnecessary X’s (X-pessimism) in Netlist. Eliminating X-optimism at RTL makes the transition to FPGA-modeling much faster by making the RTL simulations hardware accurate. Ascent XV also makes the transition to gate level simulation faster by identifying and correcting pessimism in gate level simulations. Ascent XV drives cost down by avoiding the monotonous, error-prone debug at the netlist level or within an FPGA model.

Meridian for Advanced Sign-off Verification

Meridian CDC is the fastest, highest capacity and most precise CDC solution in the market. It performs comprehensive structural and functional analysis to ensure that signals crossing asynchronous clock domains on ASIC, or FPGA devices are received reliably. With giga-gate capacity, Meridian CDC is the only solution that enables all aspects of CDC sign-off.
Meridian RDC is the fastest and most precise reset domain crossing sign-off tool in the market. It performs
comprehensive static analysis to ensure that signals crossing reset domains function reliably. Among other things, Meridian RDC identifies metastability problems arising from software and/or low power resets. Meridian RDC is the only solution that enables comprehensive reset domain crossing sign-off.
Meridian Physical CDC Option is the only solution available that provides complete glitch checking and netlist signoff.
It performs comprehensive structural and functional analysis to ensure that signals crossing asynchronous clock
domains on ASIC or FPGA devices are received reliably at the netlist gate-level. As an advanced option of Real Intent’s Meridian CDC solution that provides comprehensive analysis for RTL sign-off, it enables enhanced netlist sign-off for 500M+ gate designs.

Verix for Advanced Multimode Sign-off Verification

Verix CDC is the most precise multimode CDC solution in the market, specially architected for multimode analysis with static intent verification. It performs comprehensive CDC analysis with multiple clocks reaching the flops, allowing all possible scenarios to be covered in a single run. It is built on specialized technology that statically infers clock relationships to enable the comprehensive clock-intent management and true multimode CDC sign-off.

Common Infrastructure

iDebug is the state-of-the-art debugging environment for its suite of products for the verification of digital designs. iDebug provides an intuitive debugging experience that is universal across all Real Intent tools. It employs a database for the intelligent hierarchical analysis of design intent. It includes an integrated visualization capability, iVision, that provides design source browser, schematic and waveform visualization. The intent analyses of iDebug distinguish the root cause of issues, and minimize iterations and debug time, enabling powerful sign-off mechanisms.