| Breaks the Formal Verification Complexity Barrier | ||||||||||
| Santa Clara, Calif. - May 21, 2001-Real Intent, Inc., an EDA company that offers Intent-Driven Verification (IDV) technology, announced today a groundbreaking advance in formal Register Transfer Level (RTL) verification that breaks the inherent capacity limits of this exhaustive technique. The Company's hierarchical formal methodology, an industry first, automatically combines the formal results of lower blocks to formally verify higher blocks. By applying this scalable and hierarchical methodology, designers can formally verify functionality earlier, faster and on designs with a much larger capacity than what current commercial formal verification approaches offer. Real Intent offers this new capability in its a field-proven tool, Verix™, the EDA industry's most advanced formal RTL verification system. "Formal techniques have long held the promise of revolutionizing RTL verification of large complex ICs. However, two problems have withheld the realization of the dramatic benefits of these techniques - ease of use and capacity. Real Intent has made key advances on both fronts", said Prakash Narain, Real Intent President and CEO. "Our latest improvements remove the biggest hurdles in realizing the benefit of formal RTL verification. Our breakthrough allows our customers to continue to leverage their investment in Verix as design complexity increases." IDV Now Delivers Scalable Formal RTL Verification Real Intent breaks the formal RTL verification capacity barrier with its patent-pending scalable hierarchical verification technology. The basic approach is to verify the lower level blocks first and let the tool build up to full-chip verification by combining the verification results of the sub blocks. This allows designers to achieve exhaustive verification as the design comes together. Complete and comprehensive verification done at the next level of hierarchy requires only incremental analysis. Running incremental analysis instead of a full analysis enables the designer to perform exhaustive verification with much shorter run timesearlier in the design cycle as the design comes together. The infrastructure to manage this process is built into Verix and the user only needs to focus on the design intent. Real Intent believes that this hierarchical approach is the only scalableand viable approach that can deliver true full-chip formal RTL verification and keep up with rising design complexity. More about Intent Driven Verification (IDV) Real Intent pioneered the IDV approach that targets design violations at the earliest point in the design cycle and with the least effort. Verix is Real Intent's pioneering IDV system. The automatic Implied Intent mode of Verix allows users to formally detect design integrity violations without writing assertions or testbenches. The Expressed Intent or directed formal verification mode is implemented via in-line HDL-based assertions inserted in design code. Designers do not need to learn a new language to write these assertions. In production since July 2000, Verix has been recognized by the industry as a major breakthrough in ease of use. It is deployed in mainstream design flows at major customers throughout the world such as Broadcom, TI, ATI, VxTel, NVidia, Lightsand, Luminous Networks and others. Pricing and Availability Verix now offers hierarchical formal verification with Expressed Intent and Implied Intent checks for the Sun Solaris, HP HPUX, and Redhat Linux platforms. Pricing starts at $50,000 (USD) per year for a subscription license. About Real Intent Real Intent, headquartered in San Jose, California, offers award-winning assertion-driven formal verification products for electronic design. These products give users the capability of comprehensively verifying designs early and significantly reduce the cost of verifying integrated circuits, electronic systems and systems on a chip (SoC). |
||||||||||
|
||||||||||
|
|
||||||||||
|
|