Innovating the Intelligence of Formal Techniques for Automatic Design Verification

Published Articles

Video Interviews

Press Releases

May 26, 2010
Real Intent Showcases EDA Tools for Bridging the Verification Gap, Participates in Workshops, Presents at Verification and Test Forum at 47th DAC

May 19, 2010
Real Intent Improves Electronic Design Quality, Introduces Design-For-Test (DFT) Software

May 12, 2010
Real Intent Improves Its Fast, Low-Noise Electronic Design Linter; Ascent Lint Version 1.3 Extends High-Performance Linting to VHDL

April 14, 2010
Real Intent Attends ChipEx; Demonstrates Productivity Software for Early Functional, Clock Domain and Timing Exception Verification

April 6, 2010
Real Intent’s Real Talk Blog Addresses Verification Topics

March 16, 2010
Real Intent Attends SNUG, Demonstrates Products for Increasing Electronic Design Automation Verification Productivity

March 4, 2010
Real Intent Sponsors and Presents on “What Might Be Missing When Verifying FPGA Designs?” at the 2010 Virtual FPGA Summit

March 3, 2010
Real Intent Releases Meridian CDC Version 3.0, Strengthens Technology Leadership in Precise and Comprehensive CDC Verification

February 17, 2010
Real Intent Invites Design & Verification Community to Presentations and Product Demonstrations at DATE in Dresden, Germany

February 2, 2010
Real Intent Focuses on Proven, Cost-Effective Electronic Design Verification at DVCon

January 25, 2010
Real Intent Welcomes Professor Masahiro Fujita as Technical Advisor

January 19, 2010
Real Intent Releases Ascent Lint Version 1.2 Offering New Rule Support with Low-Noise and High-Performance Linting

January 13, 2010
Prakash Narain, Real Intent’s CEO, Presents Seminar on the Benefits of Formal Technology for Electronic Design Verification at 2010 EDSFair, Yokohama, Japan

January 6, 2010
Real Intent Focuses on Proven, Cost-Effective Electronic Design Verification at 2010 EDSFair, Yokohama, Japan

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