Real Intent Verification News
  Spring 2017  
  In this issue, we bring you…  
  • New Products & Enhancements:  Introducing our new Verix Product Family
  • Our DAC Activities:  Our President & CEO on Cooley Troublemakers Panel; Visit us at booth #928; join us at the Heart of Technology Benefit Party
  • New Webinar Available:  Solving the Reset Design Challenges of Today's SoCs
  • New Whitepapers Available:  True Multimode CDC Sign-off, FPGA, Hierarchical CDC, Reset Domain Crossing
  • New Videos Available:  RI at DAC, Introducing Verix CDC, Hierarchical CDC, Reset Domain Crossing
  • Recent Press Coverage:  Real Intent tied for #2 overall for Best EDA of 2016
  • Recent Press Releases:  Announcing the Verix product family and introducing Verix CDC
  • Recently Attended Events:  DVCon U.S. and the “Ride with the Verify Seven” Panel
  New Products & Enhancements  

Verix CDC – The first-to-market multimode CDC solution.  The new Verix product family initially offers Verix CDC, the first complete multi-mode clock-domain crossing (CDC) sign-off solution for RTL designs.  It provides one-step analysis and debug of all operating modes in an IC, and boosts productivity for SoC and FPGA design teams. It also maintains Real Intent's product leadership in delivering the industry's fastest-performance, highest-capacity, and most precise CDC solution in the market. For more on Verix CDC read the whitepaper and data sheet.

  Our market-leading Meridian CDC has been upgraded with the addition of a hierarchical CDC flow based on proprietary transparent hierarchical models that deliver scale along with our trademark precision and comprehensiveness.  
  Ascent XV Pessimism, a field-tested new product for automatic X-pessimism correction in gate-level simulation, delivers the scale and efficiency that make full-chip gate-level simulation viable with all the major simulators. With gate-level simulation widely adopted as an essential backstop in sign-off, Ascent XV Pessimism saves months of sign-off effort.  

Real Intent at DAC


Visit our DAC Booth #928

We will have a number of presentations in our DAC booth, including demonstrations of our new Verix Product Family.  To view our list of presentations and schedule a session, visit our DAC page here.

To see what John Cooley has to say about why you should come by for a visit, read his “Cheesy Must-see list” at


John Cooley Troublemakers Panel

Our President  & CEO, Prakash Narain, will be participating in John Cooley’s “Troublemakers” panel at DAC on Monday, June 19th at 3:00pm; Room 10AB, Austin Convention Center.     
The panel is free to DAC attendees, but registration is required as seating is limited.


Heart of Technology Benefit Party

This party is sure to be the swankiest party at DAC!  Donations benefit the Gary Smith Memorial Scholarship Endowment.   We are a proud sponsor and invite you to join us on June 19th at the Speakeasy, voted Austin’s "best swanky" and "best place to party.”  For more information visit here.


Webinar Available Online


If you missed our recent webinar, “Solving the Reset Design Challenges of Today's SoCs,” you can register to view it online.

With advanced system requirements, resets play an important role in software control, power saving, and debugging of the system. If not addressed proactively, RDC can result in chip failures in the field that are difficult to diagnose and expensive to fix. This webinar illustrates various reset problems through design examples to show how to deploy effective strategies to guarantee complete RDC correctness. We introduce a methodology to create reset domains, enable precise and low-noise RDC analysis, and perform efficient debug.

  New Whitepapers Available  

Verix CDC white paper: “True Multimode CDC Sign-off” – To avoid silicon failures, CDC sign-off across all operating modes is a requirement in today's SoCs. Verix CDC, with its unique static intent verification technology, is the only solution that holistically analyzes all modes in one run, and enables true multimode CDC sign-off.

FPGA white paper: “The Next Step in High-Reliability FPGA Signoff” - FPGA designs are often used in mission-critical applications where they must perform without failure.  Real Intent’s Meridian and Ascent verification products step up the FPGA design verification by introducing the new FPGA library support in all of our products in 2017. 

Hierarchical CDC white paper:  “Billion Gate CDC Sign-off Done Right” - Hierarchical CDC sign-off flow is needed to ensure quality chip level results as well as divide the volume of CDC data between the SoC and blocks. Meridian CDC enables accurate and reliable hierarchical flow with unprecedented performance and productivity gains for billion gate SoC CDC sign-off.

Meridian RDC white paper:  “Making Sure Resets Don’t Kill Your SoC” - Poor reset architecture and design can result in unreliable functional resets, causing intermittent catastrophic chip failures. Meridian RDC is the only solution in the industry that automatically extracts resets and reset domains and performs precise RDC analysis

  New Videos Available  
Our videos offer a great introduction to understanding the benefits of our products
  Recent Press Coverage  
  • DeepChip: Our CEO discusses DVCon US 2016, Portable Stimulus, the end of simulation and more
  • DeepChip: Real Intent tied for #2 overall for Best EDA of 2016; read the full article here
  • Deepchip: John Cooley’s scoop on Verix CDC here
  Recent Press Releases  

We announced our new Verix product family and introduced Verix CDC, the first complete multimode clock domain crossing (CDC) sign-off solution for RTL designs. Read the press release here.

Concept Engineering recently announced a multi-year OEM agreement with Real Intent in which Real Intent will integrate and use Concept Engineering's RTLVision™ debugger and viewer with the Real Intent Meridian and Ascent suites of RTL and gate-level analysis tools. Read the press release here.

  Recently Attended Events  
We showcased our product family at the 29th annual DVCon US, and our President and CEO, Prakash Narain participated in the panel, “Ride with the Verify Seven.”  Prakash was joined on the panel by six other verification leaders who have also grown their companies from startups to medium-sized industry players, while continuing to drive serious technology innovation.

For more information, visit

Real Intent, Inc. 990 Almanor Ave., Suite 220, Sunnyvale CA