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Real Intent May 2016 Verification News
 


Real Verification News May 2016

DAC Preview, New Meridian Constraints, Verification Trends

In this issue, we bring you a preview of Real Intent activities at the Design Automation Conference in Austin Texas, June 6-9; news about the latest release of our Meridian Constraints product, a report on why a customer switched from SpyGlass to Real Intent, and a video update on verification trends. Details for all of this and more fun stuff are below.

Thoughts From Prakash Narain, President and CEO…

Technological innovation drives electronic design automation. It’s doubtful anyone at the inception of our industry in the early 1980s would have believed that we can handle giga-scale verification of SoCs now! My work as a developer, microprocessor designer, verification tools designer and user led me to found Real Intent as a company focused on static verification tools to address the growing complexity of verifying advanced SoCs and FPGAs. I’ve seen the automation and ease-of-use of design and verification tools evolve from infancy to full maturity. In fact, it’s now impossible to sign-off on a design without using some type of formal verification. But the huge advances in speed, capacity and complexity of today’s medical, automotive and consumer-based applications beg the question, “What’s next for EDA?” Even though the drumbeat of Moore’s Law may be slowing a bit, the demand for larger, even more complex chips isn’t. Therefore, design and verification tool innovation must keep pace. To achieve this goal will require more design automation research and new startup activity. We’ll need closer ties between the EDA industry and universities to spark creative thinking and source new talent. Finally, we’ll need to foster closer collaboration throughout the entire design ecosystem. I view all four as vital next steps for the design industry.
 
I would like to invite you to come visit us in Booth #527 at DAC Austin to see our latest technical presentations and enjoy a fresh espresso coffee. To choose your technical presentation click here.
 

Fun and Fast RTL Sign-off at the 53rd DAC in Austin, TX

This year we’re bringing our advanced Ascent and Meridian technology, EDA expertise and espresso energy to the 53rd DAC in Austin. In the spirit of faster verification and design success, come see us in Booth #527 for the latest information about our Ascent tools for static RTL verification, and our Meridian tools for CDC and SDC sign-off at the RTL and gate-level. You can view technical presentations about our latest advancements, proven on giga-gate SoC and FPGA designs.  Click here to make an appointment for our private suite presentations.

Completing a quick verification survey enters you into drawings for a cool Roku 4 streaming player and an Amazon Echo wireless speaker and voice commander. You can Espresso Yourself and enjoy a high-speed coffee from our DeLonghi Magnifica super-automatic coffee machine, to celebrate faster verification and design. Visiting Real Intent and OpenText (Booth #638), our “Espresso Yourself” partner at DAC, and getting a ticket stamped by both companies enters you into drawings to win $100 Amazon Gift Cards. We’ll top off your visit with a rose as a sweet thank-you gift.

New Release of Meridian Constraints with Functional Analysis

This month we announced the next release of Meridian Constraints for comprehensive timing constraint verification and management. This software release adds new and unique functional analysis, data-driven debug, and support for distributed design development, maintaining Real Intent's product leadership in providing delivering the industry's fastest sign-off solutions.

The new functional analysis of timing exceptions needed for untimed paths in logic designs, including false paths and multi-cycle paths.  Untimed paths require separate verification that existing synthesis and static timing analysis tools do not validate. The newly added functional analysis accelerates the sign-off of timing exceptions by dramatically reducing by 50-percent the number of paths needing formal verification.

Click here to read further details in the announcement.

The Switch from Atrenta to Real Intent for CDC, Lint, and X-prop

John Cooley’s Deepchip.com web-site likes to publish end-user experience with various EDA tools.  On May 6, he published a posting on why a designer switched from Atrenta SpyGlass to Real Intent for CDC, Lint, and X-propagation analysis.  His report details the reasons for converting to our best-in-class tool suite.

Click here to read the entire report on CDC, Lint and X-propagation.

Verification Trends Video Interview by SemIsrael

Pranav Ashar, CTO at Real Intent, was interviewed last month by SemIsrael, Israel’s leading semiconductor design and development portal, about the latest trends in the world of SoC and FPGA verification. He covered the following questions:
  • What is the current trend driving verification?
  • How are designers meeting these challenges?
  • What static verification solutions are needed?
  • What about debug?
  • What’s next in SoC and FPGA verification?
View the video clips for each question by visiting the Real Intent blog article: Verification Coffee Break – Where are We Going? 

Real Intent Named as One of 20 Most Promising Semiconductor Companies for 2016

Real Intent was selected by SiliconIndia as one of its “20 Most Promising Semiconductor Companies - 2016.” Its interview of Prakash Narain in the April 2016 edition was featured in the article, “Real Intent: Accelerating the Verification of Digital ICs,” and succinctly describes the benefits of our products.



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Video Update

Video: New 2015 Lint

Video: New 2015 Lint

Video: New 2015 Lint
Video: New 2015 Lint
X-pessimism: Why do We Care; What are the Wrong and Right Fixes for it?

Video: New 2015 Lint
Why A New Gate-level Physical CDC Verification Solution is Needed

In the News

Real Intent Delivers Next Release of Meridian Constraints for Sign-Off of SoC Designs

Real Intent Delivers Major Innovation in Clock Domain Crossing Sign-off
of SoC Designs



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