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Real Intent February 2015 Verification News
 


Real Verification News February 2016

DVCon, Verification Seminar, CDC Blog Series, and New Videos

In this issue, we highlight our industry experts panel at the Design and Verification Conference (DVCon) in Silicon Valley, an upcoming Verification Seminar, a blog series on CDC Verification of Fast-to-Slow Clocks, and two new videos.

Thoughts From Prakash Narain, President and CEO…

The scope of verification is changing. Now it’s necessary to do verification at pre-RTL integration,  full RTL and post-synthesis stages. The driving force for this expanded scope is the aggregation of heterogeneous IP from multiple sources. A successful verification approach must support successive refinement at the IP stage, as well as verification after all the units and blocks -- some we created and some from third parties -- have been integrated at the RTL stage of development. Integrating complex digital logic with third-party IP makes it mandatory to verify clock-domain crossing and reset-domain crossings for sign-off because CDC errors are challenging to debug. Verifying at this stage of development saves valuable debug time after implementation. It requires either full-chip capacity and performance for overnight runs, or a robust hierarchical flow that doesn’t sacrifice accuracy or precision for faster throughput. Post-RTL analysis also is needed to ensure that netlist optimization has not broken RTL functionality and introduced glitches. Only a mix of structural and formal technologies -- what we call static analysis -- can deliver the necessary performance and confidence required for successful sign-off.

Our last exhibition events were in Japan, China, Europe and Israel. I hope you’ll come visit us next month in Silicon Valley, USA at DVCon (Feb. 29 - Mar. 2), and CDNLive (Apr. 5-6). We are also hosting a one day seminar in Israel (Apr. 5). You’ll see our Ascent and Meridian tools for the comprehensive, unsurpassed verification and sign-off support you rely on.

DVCon Panel: Emulation + Static Verification Will Replace Simulation

If you’re attending DVCon in Silicon Valley, be sure not to miss a lively panel discussion organized by Real Intent and moderated by Jim Hogan of Vista Ventures on Wednesday, Mar. 2 from 1:30 to 2:30 p.m.at the DoubleTree Hotel in San Jose, Calif.

With emulation and static verification on a steep upward spiral, some believe the verification paradigm of the future will be to invest in high-end targeted static verification tools to get the design to a very high quality level, followed by very high-speed emulation or FPGA-prototyping for system-level functional verification. But where does that leave RTL simulation? Gate-level simulation already is marginalized, doing basic sanity checks. Will RTL simulation follow that example? A panel of technical experts from Imagination Technologies, Google, Cavium, Dialog Semiconductor, Oregon Angel Fund and Real Intent will explore and debate what the future verification paradigm will be. For more information, click here.

One-day Verification Seminar in Israel

On April 5, at the Dan Accadia Hotel, Herzliya, Real Intent will host a day-long verification seminar. Our technologists, including Oren Katzir, vice-president of Applications Engineering will cover the following topics:
  • RTL sign-off
  • Advanced clock-domain crossing analysis
  • Timing constraints verification
  • Accelerating debug with lint and autoformal
  • X-safe design from RTL to netlist
  • Crossing glitches and Resets
The Customer Tracks in the schedule will highlight real-world experiences with digital verification.  Additionally, there will be opportunities for networking at the various meal and break times.

To learn more about the seminar, click here.

CDC Verification of Fast-to-Slow Clocks

Recently, we re-published a short blog series by Dr. Roger B. Hughes that addresses the issue of doing clock domain crossing analysis where the clocks differ in frequency, and the use of three different techniques for a complete analysis.

Introduction

CDC checking of any asynchronous clock domain crossing requires that the data path and the control path be identified and that the receive clock domain data flow is controlled by a multiplexer with a select line that is fed by a correctly synchronized control line.  Meridian CDC will always identify all the data and associated control paths in a design and will ensure that the control signals passing from a transmit clock domain to an asynchronous receive clock domain are correctly synchronized.  There are three separate techniques that are used within Meridian CDC: structural checking, formal checks and simulation-based injected metastability checks. Click on the links to read further.
CDC Verification of Fast-to-Slow Clocks - Part 1: Structural Checks
CDC Verification of Fast-to-Slow Clocks - Part 2: Formal Checks
CDC Verification of Fast-to-Slow Clocks - Part 3: Metastability Aware Simulation

New Videos on CDC and X-Verification

The first new video is a conversation with Oren Katzir, VP of Applications Engineering. He shares what has changed in CDC verification over the last few years, the new Meridian CDC and Physical CDC products; and what is his favorite feature of the Meridian tools.

The second video is an interview with  Lisa Piper, Sr. Marketing Manager. She discusses chip initialization and reset analysis, why the current methods to address it are inadequate, and how the Ascent X-Verification system employs static analysis to deliver an effective solution. Customer experiences are also included.



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Video Update
Video: New 2015 Lint
X-pessimism: Why do We Care; What are the Wrong and Right Fixes for it?

Video: New 2015 Lint
Why A New Gate-level Physical CDC Verification Solution is Needed

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