Innovating the Intelligence of Formal Techniques for Automatic Design Verification

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Ascent

Ascent Benefits:
  • Best verification ROI, catch most design bugs early without testbench
  • Automatically detect 50% of bugs, improve block level design quality, significantly reduce project cycle

Features:
  • Advanced LINT analysis
    • Syntax/semantic errors, synthesis/simulation mismatch, naming conventions etc
  • Exhaustive formal sequential analysis
    • State reachability, single or pair-wise state deadlock, dead code, synthesis pragma violations, etc
  • Leading edge language support
    • Verilog, VHDL, System Verilog, PSL, SVA

Ascent Family Data Sheets:
English    Japanese

Ascent Lint Data Sheets:
English    Japanese

Ascent IIV Data Sheets:
English    Japanese

Ascent ABV Data Sheets:
English    Japanese