DAC 2017 Real Intent Booth Appointment Signup
|Come to DAC and see how Real Intent has taken a leap forward with these new advances:
Our technical presentations will bring you up to date with our new product releases that have been proven on giga-gate SoC and FPGA designs. After reviewing the presentation abstracts please fill out the signup form below to book your appointment with Real Intent at booth #928.
Introducing Verix CDC: Industry’s most precise multimode CDC solution specially architected for multimode analysis with static intent verification
Real Intent introduces Verix CDC, the revolutionary and most precise multimode CDC solution in the market. Verix CDC performs comprehensive CDC analysis using multiple clocks reaching the flops, so all possible scenarios are covered in single multimode run. It is built on a specialized static intent technology that interprets clock intent and enables the most comprehensive clock intent management and multimode CDC Sign-off. The result is a manifold reduction in the CDC signoff effort for today’s SoCs. Schedule a Time.
How to Accelerate Your RTL Sign-off
Real Intent will present the elements of a best-in-class solution for the accelerated RTL sign-off of SoC and FPGA designs. A full suite of static verification risks will be covered including: RTL static and formal intent verification; reset analysis and optimization; CDC sign-off; RDC sign-off and X-safe design analysis. Schedule a Time.
Most precise static and formal RTL Analysis with Ascent Lint and AutoFormal
Ascent Lint, together with AutoFormal, continues to be the industry’s fastest and lowest-noise RTL functional verification solution. We will present the latest advances including support for VHDL 2008 and SystemVerilog 2012, and the new integrated debugger. Come hear about the latest new linting rules and how new advances in Automatic Formal yields higher capacity and performance than ever before. Schedule a Time.
Meridian CDC with Hierarchical CDC flow
Meridian CDC continues to be the fastest, highest capacity and most precise CDC sign-off solution in the market. At DAC 2017, we present industry’s best Hierarchical CDC capability that allows users to perform CDC verification on billion-gate SOCs within a matter of hours. The flow enabled by transparent model database provides unprecedented productivity gains, high accuracy, and low noise results with seamless SoC debug. You will not want to miss seeing the latest in advanced CDC sign-off. Schedule a Time.
Ascent XV with Advanced Gate-level Pessimism Analysis
Ascent X-Verification System (XV) provides a comprehensive static solution for making an RTL design X-robust and eliminates error-prone debug at the netlist level. At DAC, discover the very latest in X-propagation verification. See how to identify unnecessary resets at RTL. Learn a cost effective approach for tackling pessimism accurately in your gate level simulations. Schedule a Time.
Introducing industry’s most accurate Reset Domain Crossing solution
Meridian RDC is the lowest noise and most precise reset domain crossing sign-off tool in the market. It performs efficient and thorough static analysis to ensure that signals crossing reset domains function reliably. Among other things, it identifies metastability problems arising from software and/or low power resets. Meridian RDC is the only solution that considers cascading effects of improper reset design and enables comprehensive reset domain crossing sign-off. Schedule a Time.
Gate-Level CDC Sign-off with Meridian Physical CDC
RTL CDC sign-off assumptions may not be valid because of logic synthesis and power optimizations. Meridian Physical CDC is the only solution that ensures complete gate-level sign-off. See how a new architecture leverages results of RTL CDC sign-off and performs efficient and incremental CDC analysis at gate level. Schedule a Time.