SUNNYVALE, CA, October 29, 2018 — Real Intent, Inc., a leading provider of SoC and FPGA sign-off verification solutions, today announced Meridian RXV, a new tool to tackle “X” sources and design initialization up-front at the Register Transfer Level (RTL), thereby accelerating reset design, validation and sign-off.
“Reset design complexity is increasing rapidly in modern SoCs and reset-initialization bugs are starting to escape, causing tape-outs to be respun. As a result, customers are looking for faster and more reliable sign-off of resets,” stated Prakash Narain, Ph.D., Real Intent President and CEO. “Meridian RXV analyzes design initialization and exposes the X sources and their functional impact. With its multi-million gate capacity and super-fast Static Analysis, Meridian RXV is the first product to enable X-propagation analysis on a practical scale.”
While hardware resets can be used to initialize registers to known values, resetting every flop or latch is challenging, and not always necessary. Meridian RXV includes a Reset Audit that provides an accurate understanding of the design initialization requirements and status.
After reviewing Reset Audit information, designers can choose to optimize the reset scheme for the design. Reset optimizations in Meridian RXV can determine an additional minimal number of reset flops needed to increase the design’s initialization percentage. Alternately, RXV can also identify flops that do not need to be explicitly reset while maintaining the initialization, which helps reduce routing complexity, area and power consumption.
Meridian RXV delivers a comprehensive report that highlights the susceptibility of a design to the masking of functional bugs due to X-optimism in RTL simulation. All X-sources in the design are automatically identified through structural analysis as well as X-accurate formal Reset Audit. The report shows nets in the design that are sensitive to X-optimism due to the propagation of an X from said X-sources, and provides a trace from each X-Optimism net to a relevant X-source and debug information with links to the RTL source code.
Meridian RXV provides comprehensive reports for review of the Reset Audit, Reset Optimization and X-Optimism Analysis. It also has a powerful integrated graphical interface that shows debug paths, facilitates waivers of X-sources, and provides links for source code navigation.
For more information on Meridian RXV, a datasheet is available.
Meridian RXV is available now. Pricing depends on product configuration. For more information, please email firstname.lastname@example.org
Real Intent is the industry leader in static sign-off of digital designs. Top-tier companies worldwide rely on Real Intent’s EDA software to accelerate early functional verification and sign-off at RTL as well as gate-level. Its intent-driven static technology powers solutions for clock and reset domain crossing analysis (CDC, RDC), Sign-Off quality clean RTL code, and X-pessimism correction, to ensure design success for SoCs and FPGAs. Real Intent products lead the market in performance, capacity and accuracy, enabling a measurably faster time to tape out. Por more information, visit www.realintent.com
CDC: Clock Domain Crossing
EDA: Electronic Design Automation
FPGA: Field-Programmable Gate Array
RDC: Reset Domain Crossing
RTL: Register Transfer Level