Ascent Lint uses static analysis to enforce coding guidelines, enabling you to catch functional issues early — prior to simulation — and ensure high quality RTL. Its high performance and capacity enable both block level and full chip analysis.
Ascent AutoFormal, a multimillion gate capacity formal linting tool, identifies RTL design bugs using formal sequential analysis, expanding on Ascent Lint‘s syntax, semantic, and style checks.
Verix DFT is a high capacity, multimode DFT static sign-off tool, which runs a comprehensive set of DFT rules to rapidly identify RTL and gate-level design violations to help designers improve scan testability and coverage.
Meridian RXV X-propagation sign-off tool performs accurate audit of design initialization and provides useful debug capability. It prevents inaccurate RTL simulation by identifying potential X-optimism.