DAC2019-05-24T00:04:15-07:00

 

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Ascent Lint

Real Intent’s Ascent Lint is a high capacity and performance linting solution for early RTL sign-off.  It runs precise, high-impact checks resulting in more actionable debugging and less report filtering.  The latest release of Ascent lint is now ISO-26262 certified for use in automotive systems design and supports VHDL-2008.

Ascent AutoFormal

Real Intent’s Ascent AutoFormal is an automatic fully static verification tool.  It detects difficult bugs with high accuracy and low noise, all without a test bench.  These checks identify issues with FSM deadlock and transition reachability, as well as unreachable blocks and full_case / parallel_case violations.  The latest release introduces a 10x performance speedup and improved capacity over previous versions of the tool.

Meridian CDC

Meridian CDC is the highest capacity, performance and precision static sign-off clock domain crossing tool in the market today.  Asynchronous clock domain analysis is key to design success in today’s integrated SoC development flows, ensuring data is not lost or corrupted as it travels between components. Meridian CDC’s hierarchical approach enables billion gate analysis within hours.  The most recent releases of Meridian CDC are ISO-26262 certified for use in automotive hardware development flows.

Meridian RDC

Meridian RDC is a high precision static sign-off solution for reset domain crossing analysis. Its powerful analysis rapidly identifies many classes of reset domain crossing failures, such as metastability from low power domains as well as reset glitch conditions.  The latest release incorporates hierarchical analysis and parallelized runs for dramatic run time performance.  This year, Meridian RDC add ISO-26262 certification for use in automotive electronic systems development.

Meridian RXV

Meridian RXV is a sign-off quality X-impact analysis engine for design initialization auditing.  It identifies areas where RTL simulation may not match synthesis results and performs reset optimization analysis.  This analysis identifies potential simulation issues prior to test bench generation and examines design initialization / power and routing trade-offs.

Verix CDC

Real Intent’s Verix CDC improves upon its industry leading Meridian CDC tool by incorporating multimode clock analysis into a single run.  Specifically architected for this unique class of analysis, Verix CDC’s engines identify and interpret complex clocking structures while eliminating noise by automatically rejecting impossible clock combinations.  The multimode debugging analysis combines all clock modes into a single, unified report, eliminating the many duplicate runs required by all single mode CDC solutions today.

Verix PCDC

Verix Physical Clock Domain Crossing (PCDC) tool takes CDC analysis to gate-level.  Assumptions made during RTL CDC analysis can be invalidated during synthesis and power optimization.  Multimode cloc analysis limits the error prone separate manual jobs required by single mode CDC tools.  Verix PCDC makes gate-level analysis incremental to RTL CDC by leveraging the Verix CDC flow.  This makes identifying potentially design-killing gate-level CDC failures easy within the integrated debug environment.  Verix CDC and Verix PCDC combine to create a complete RTL / gate-level CDC sign-off flow.

Verix SimFix

Real Intent’s Verix SimFix performs X-Pessimism correction to enable accurate gate-level simulations for thorough verification sign-off.  Without SimFix, gate-level simulation is compromised by inaccurate random initialization or costly synthesis configurations, both of which are error prone and require intensive debugging effort.  Verix SimFix supports hierarchical flows to enable SoC-scale verification sign-off.