Solving the Reset Design Challenges of Today’s SoCs
Sanjay Thatte, Senior Technical Marketing Manager from Real Intent
Ensuring Robust RTL Sign-off for Stratix® FPGA and SoC Designs
Rama Venkata from Intel’s Programmable Solutions Group
Ramesh Dewangan from Real Intent
Ramesh Dewangan at DVClub Shanghai: “Shortening Debug with New Methods in Static Verification.“
“Even with high degree of design reuse, verification continues to be the long pole in design development. This has created a huge stress in current functional verification methodologies, which rely primarily on dynamic verification. Design complexity has made debug cycle times unpredictable and longer.
The static verification techniques have been successfully used in targeted problem domains like clock domain crossing, reset optimization, X-optimism/pessimism, FSM integrity and so on. My presentation provides specific design examples and how the static techniques solves them more efficiently.
Not every verification problem is a nail that you need big hammer for. Simulation is too expensive and time consuming for a majority of verification problems. Why not ease the pain by using faster, targeted, and exhaustive static verification techniques to shorten your verification debug cycle?”
Automatic RTL Verification with Ascent IIV: Find Bugs Before Simulation
Ascent IIV Autoformal is an early functional verification tool that provides immediate return on investment by quickly finding elusive bugs in RTL blocks. Ascent IIV Autoformal can improve verification efficiency substantially and detect up to 50% of design functional errors prior to testbench development and simulation. Ascent IIV Autoformal performs comprehensive verification using automatic check formulation followed by deep-sequential formal analysis.
The webinar will introduce tool setup, the kinds of difficult bugs that can be found with the tool, and demonstration of its latest features.
Please fill out the form, with your company email address, to view the webinar.