Webinars

Webinars

Solving the Reset Design Challenges of Today’s SoCs

Sanjay Thatte, Senior Technical Marketing Manager from Real Intent

Ensuring Robust RTL Sign-off for Stratix® FPGA and SoC Designs

Technical presenters:
Rama Venkata from Intel’s Programmable Solutions Group
Ramesh Dewangan from Real Intent

 

Ramesh Dewangan at DVClub Shanghai: “Shortening Debug with New Methods in Static Verification.“

“Even with high degree of design reuse, verification continues to be the long pole in design development. This has created a huge stress in current functional verification methodologies, which rely primarily on dynamic verification. Design complexity has made debug cycle times unpredictable and longer.

The static verification techniques have been successfully used in targeted problem domains like clock domain crossing, reset optimization, X-optimism/pessimism, FSM integrity and so on. My presentation provides specific design examples and how the static techniques solves them more efficiently.

Not every verification problem is a nail that you need big hammer for. Simulation is too expensive and time consuming for a majority of verification problems. Why not ease the pain by using faster, targeted, and exhaustive static verification techniques to shorten your verification debug cycle?”