Real Intent is the leading provider of EDA software to accelerate Early Functional Verification and Advanced Sign-off of digital designs. It provides comprehensive clock-domain crossing verification, advanced RTL analysis and sign-off solutions to eliminate complex failure modes of SoCs. The Meridian and Ascent product families lead the market in performance, capacity, accuracy and completeness.
Real Intent was founded in 1999. The initial focus of the company was formal verification products (assertion based verification). Although formal technology is still used in our products, in 2009 the company took a Best-in-Class Solution direction that has led to our current product offerings in CDC, lint, design constraint verification and X-verification.
The company is financially very stable. Bookings and revenues more than doubled in the fiscal year 2012. The company is funded by Andy Bechtolsheim, founder of Sun Microsystems as well as many other successful semiconductor companies. He was an investor in EDA companies including Magma DA and Apache, and an initial investor in Google. Mr. Bechtolsheim is chairman of Real Intent’s board of directors.
We have more than 40 major semiconductor companies using our products on a worldwide basis, including some of the largest companies developing ICs for mobile, networking, telecommunication and display graphics, among other applications.
We place high priority on customer support and have excellent customer references.
The technology drivers for our company’s growth and success include:
- ability to provide sign-off quality products that are accurate and complete in coverage,
- significantly better performance and capacity,
- ability to run designs exceeding 500M gates with 5-20x higher performance over similar products,
- concise, lower noise reports that enable efficient debug of designs,
- advanced, differentiated technology such as X-safe verification.
Real Intent has sales offices in the USA and Japan, and distributors in Europe, India, Israel, Korea and Taiwan.
Real Intent offers two product families – Ascent for early functional verification before simulation or synthesis; and Meridian for advanced sign-off verification not possible with simulation or static timing analysis.
Ascent for Early Functional Verification
Ascent Lint is the industry’s fastest and lowest-noise RTL lint solution. It includes smart rules that perform syntax and semantic checks for today’s complex System-on-Chip (SoC) designs. Ascent Lint is unique in the industry in terms of delivering high capacity, comprehensiveness and ease of debug.
- Highest performance Lint product available in the market; up to 20x faster than similar products.
- Low noise, comprehensive reporting; order of magnitude fewer messages without loss of coverage
- Offers easy adoption, use and customization
- Fast and powerful debugging capability with cross-probing to RTL design source; pinpoints the exact source of issues
- Provides GUI for rule selection, waiving, and customization, as well as debugging the violations report
- Incremental analysis indicates new violations compared to a previous run
Ascent AutFormal is an early functional verification tool that automatically finds elusive bugs in RTL without the need for writing assertions or testbenches. It performs comprehensive verification using automatic check formulation followed by deep-sequential formal analysis. Ascent AutoFormal can improve verification efficiency substantially and detect up to 50% of design functional errors prior to testbench development and simulation.
Ascent X-Verification System (XV) addresses X-propagation issues, including isolating potential X-optimism at RTL and the correction of unnecessary X’s (X-pessimism) in Netlist. Eliminating X-optimism at RTL makes the transition to FPGA-modeling much faster by making the RTL simulations hardware accurate. Ascent XV also makes the transition to gate level simulation faster by identifying and correcting pessimism in gate level simulations. Ascent XV drives cost down by avoiding the monotonous, error-prone debug at the netlist level or within an FPGA model.
Meridian for Advanced Sign-off Verification
Meridian CDC is the fastest, highest capacity and most precise CDC solution in the market. It performs comprehensive structural and functional analysis to ensure that signals crossing asynchronous clock domains on ASIC, or FPGA devices are received reliably. With giga-gate capacity, Meridian CDC is the only solution that enables all aspects of CDC sign-off.
- Highest capacity and highest performance tool available in the market
- 5-20x faster run times versus similar products
- 98M gate design with 16 clock domains (200+ total clocks defined) completed top level, flat in 5 hours
- Lowest Noise, Smart Reporting
- Strong emphasis on achieving correct environment setup
- Crossing-based analysis ensures accuracy
- Up to 10x reduction in warnings versus similar products with no loss in error coverage
- Integration with formal and simulation for complete sign-off
- Complete CDC verification solution
- Only formal solution capable of frequency-independent clock analysis
- Simulation provides backup to formal for higher capacity analysis
- Complete full-chip CDC sign-off including both RTL and Netlist support
- Automatic hierarchical analysis for full chip verification
Meridian Constraints is the most comprehensive constraint management solution in the market. It offers high-performance constraint validation, template generation, coverage analysis, equivalence checking and timing exception verification capabilities designed to provide users with ultimate confidence in the timing constraints employed across all phases of the implementation flow.
Real Intent, and the Real Intent logo are registered trademarks of Real Intent, Inc.