DAC Registration2019-05-23T04:27:22+00:00

Register to Visit Real Intent @ DAC

Learn more about how our static sign-off tools can help you accelerate your early functional verification of digital designs.
Exhibit days: June 3 to June 5, 2019
Meeting hours:  9 am – 6 pm

  • This field is for validation purposes and should be left unchanged.

Ascent Lint

  • High capacity & performance RTL linting & sign-off
  • Precise, high-impact checks — more actionable debugging & less noise
  • ISO-26262 certified & Supports VHDL-2008

Ascent AutoFormal

  • Automatic fully static verification tool, with new 10X performance & multi-million gate capacity
  • High accuracy, low noise bug detection – without a test bench
  • Identifies root cause errors, such as FSM deadlock & unreachable blocks

Meridian RXV

  • Sign-off quality X-impact analysis for design initialization auditing
  • Identifies where RTL simulation may not match synthesis results & performs reset optimization analysis
  • Identifies potential simulation errors before test bench generation & examines design initialization/power & routing trade-offs

Meridian CDC

  • Industry’s highest capacity, performance & precision static sign-off clock domain crossing tool
  • Hierarchical approach enables billion gate analysis within hours
  • ISO-26262 certified

Verix CDC

  • Multimode CDC covers all clocking scenarios into a single run
  • The unified simultaneous analysis delivers exhaustive confidence
  • Unified report eliminates the duplicate runs required by single mode CDC tools

Verix PCDC

  • Supplements RTL CDC sign-off for changes during synthesis and power optimization
  • Eliminates potential design-killing gate-level CDC failures
  • Verix CDC & Verix PCDC combine for complete RTL through gate-level CDC sign-off

Meridian RDC

  • Low noise, high precision reset domain crossing static sign-off
  • Rapidly identifies many classes of reset domain crossing failures, including metastability & glitch conditions
  • Hierarchical analysis & parallelized runs for accelerated runtime
  • ISO-26262 certified

Verix SimFix

  • Automatic X-Pessimism correction enables accurate gate-level simulations for thorough verification sign-off
  • Minimizes intensive debugging during gate-level simulation due to inaccurate random initialization or costly synthesis configurations
  • Supports hierarchical flows to enable SoC-scale verification sign-off