Solving the Reset Design Challenges of Today's SoCs

Join our Reset Domain Crossing (RDC) webinar on Tuesday May 9

11:00AM-12:00PM Pacific Time  |  1:00-2:00PM Central Time |  2:00-3:00PM Eastern Time

Solving the Reset Design Challenges of Today's SoCs

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With advanced system requirements, resets play an important role in software control, power saving and debugging of the system. Poor reset architecture can result in unreliable functional resets, causing intermittent catastrophic chip failures. All modes of Reset functionality failure are impossible to catch in static solutions like STA, Clock Domain Crossing (CDC) tools, or through simulation. If not addressed proactively, RDC can result in chip failures in the field that are difficult to diagnose and expensive to fix.

This webinar will illustrate various reset problems through design examples to show how you can deploy effective strategies to guarantee complete RDC correctness. We will introduce a methodology to create reset domains, enable precise and low-noise RDC analysis, and perform efficient debug.

This analysis ensures:

  • Asynchronous resets that are crossing reset domains will not cause metastability
  • Reconverging synchronized resets are functionally correlated
  • Asynchronous resets are glitch-free
  • Reporting of good vs. bad reset design is differentiated with minimum noise
  • Violations are pinpointed for efficient debugging

Sanjay Thatte, Senior Technical Marketing Manager from Real Intent, will be the presenter.

You can join our GoToWebinar session by using a Mac, PC or a mobile device.
For those who can not attend our live session, we will provide a recording.



Please use @company email address to ensure approval.

After registering, you will receive a confirmation email containing information about joining the webinar.

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