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	<title>Real Talk</title>
	<link>http://www.realintent.com/real-talk</link>
	<description>The Real Intent Blog</description>
	<lastBuildDate>Sat, 31 Jul 2010 03:57:02 +0000</lastBuildDate>
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		<title>Hardware-Assisted Verification Usage Survey of DAC Attendees</title>
		<description><![CDATA[Tradeshows and technical conferences serve as great places to survey the verification landscape and the Design Automation Conference in June was no exception.
EVE took the opportunity to poll visitors to its booth with a survey similar to the one used at EDSFair in Japan earlier in the year.  Interestingly enough, some of our findings in [...]]]></description>
		<link>http://www.realintent.com/real-talk/217/hardware-assisted-verification-usage-survey-of-dac-attendees</link>
			</item>
	<item>
		<title>Leadership with Authenticity</title>
		<description><![CDATA[An interesting title…What is leadership with Authenticity?
Well, let’s discover…first of all let’s break it down; we will start out by talking about leadership.
Is leadership telling people what they want to hear to keep them going the direction you think they should go? Or is leadership just taking flight and hoping that people follow?  Wikipedia defines [...]]]></description>
		<link>http://www.realintent.com/real-talk/209/leadership-with-authenticity</link>
			</item>
	<item>
		<title>Clock Domain Verification Challenges: How Real Intent is Solving Them</title>
		<description><![CDATA[With chip-design risk at worrying levels, a verification methodology based on just linting and simulation does not cut it. Real Intent has demonstrated that identifying specific sources of verification complexity and deploying automatic customized technologies to tackle them surgically has benefit. Automatic and customized don’t go together at first glance. Whereas automatic deals with maximizing [...]]]></description>
		<link>http://www.realintent.com/real-talk/206/clock-domain-verification-challenges-how-real-intent-is-solving-them</link>
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	<item>
		<title>Building Strong Foundations</title>
		<description><![CDATA[I recently joined Real Intent with over 10 years of experience developing and supporting assertion-based methodologies and have seen the technology move from research toward the mainstream.   Formal technologies have proven to have a lot of value for functional verification and for coverage, but having to learn evolving assertion languages and techniques has slowed the [...]]]></description>
		<link>http://www.realintent.com/real-talk/198/building-strong-foundations</link>
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		<title>Celebrating Freedom from Verification</title>
		<description><![CDATA[Happy Fourth of July!  If you’re celebrating Independence Day today, chances are you have the time to do so because of a set of tools that freed you from the drudgery of endless verification cycles.
Yes, let’s give thanks as an industry to the plethora of commercial tools that reduce the amount of time consumed by [...]]]></description>
		<link>http://www.realintent.com/real-talk/195/celebrating-freedom-from-verification</link>
			</item>
	<item>
		<title>My DAC Journey: Past, Present and Future</title>
		<description><![CDATA[PAST
I have a unique prospective on DAC since I have attended DAC in many different capacities over the last 15 years: as a poor student, a lucky customer, an excited vendor participant, an independent consultant, a free spirit and a hard working vendor organizer.  The following log describes the many DACs that I have attended and [...]]]></description>
		<link>http://www.realintent.com/real-talk/183/my-dac-journey-past-present-and-future</link>
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	<item>
		<title>Verifying Today’s Large Chips</title>
		<description><![CDATA[Today’s chips are pushing the verification envelope with their size, integrated system-level functionality, and the nano-scale-driven bubbling up of previously second-order considerations. Also, diminishing returns from geometry-shrinks force designers into ever more aggressive control optimizations for timing and power, and manufacture-test considerations require fancier DFT structures on chip. The visible manifestation of these effects has [...]]]></description>
		<link>http://www.realintent.com/real-talk/180/verifying-today%e2%80%99s-large-chips</link>
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	<item>
		<title>You Got Questions, We Got Answers</title>
		<description><![CDATA[Have you ever worried about:

Missing real bugs in a 10,000-line verification report?
Whether your design will function as intended?
Why there are RTL and netlist simulation mismatches?
When you can sign-off on clock domain crossing verification?
Whether your RTL has enough test coverage?
If you design constraints are correct?

DAC is an excellent time to connect with EDA vendors to get [...]]]></description>
		<link>http://www.realintent.com/real-talk/174/you-got-questions-we-got-answers</link>
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	<item>
		<title>Will 70 Remain the Verification Number?</title>
		<description><![CDATA[It’s that time of year again.  The design automation community is about to descend on Anaheim for the yearly conference.  The build up of anticipation, the buzz and the extra effort preparing for our booth have me pondering the topic of verification.
With verification consuming 70% of the design cycle, will 70% of the exhibitors at [...]]]></description>
		<link>http://www.realintent.com/real-talk/167/will-70-remain-the-verification-number</link>
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	<item>
		<title>A Model for Justifying More EDA Tools</title>
		<description><![CDATA[One of the overwhelming issues facing the EDA community is the need and desire to increase total sales. One of the greatest hurdles in the ongoing chase to get more seats is the inability to convert the design software budget dollars into new seat licenses. Although most large companies have more than adequate dollars budgeted [...]]]></description>
		<link>http://www.realintent.com/real-talk/164/a-model-for-justifying-more-eda-tools</link>
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