In Memory of Dr. Miles Copeland: Innovator and Mentor

miles-copelandI had just learned this week that my mentor into the world of EDA, Dr. Miles Copeland had passed away recently.

At Carleton University in Ottawa, Canada, Copeland was the former chair of the Department of Electronics and Professor Emeritus in the Faculty of Engineering and Design. He was an IEEE Fellow and was known for his passion for teaching and research innovation.

In addition to educating two and a half generations of electrical engineers, Copeland had established Carleton’s research capacity in the area of analog and radio frequency integrated circuit design, including the development of computing techniques to enable and reinforce research and learning.

The focus on computing techniques was how I came to work with Copeland.

As a recent graduate of the Department of Computer Science with a focus on computer hardware, I was hired by Dr. Copeland, as a research engineer, to port SPICE, a 14,000 line Fortran program, into a 16-bit microcomputer (Corvus Concept) that was based on the Motorola 68000 micro-processor. This allowed students to simulate their circuits before fabricating them in-house on the University’s 2-inch wafer line. Later on, I worked with Copeland on extending a mixed-analog digital simulator, SPLICE, to handle mixed sampled data circuits, specifically switched-capacitor filters.  We published the research in an IEEE journal that led me to be hired to work on the PSPICE simulator in California.  I owe my entire career in high-tech to Miles Copeland.

Copeland was actively involved in consultation and research collaboration with industry, notably at Nortel, Bell Northern Research and General Electric. His widely used research innovations include groundbreaking work that enabled the design of fully integrated radios. His research was also key to the design of modern telecommunications circuits that are used in today’s personal communications devices and wireless data communication

Over his distinguished teaching career, Copeland supervised nearly 50 masters and PhD students.

In recognition of his achievements, Copeland recently received the 2016 Institute of Electrical and Electronics Engineers (IEEE) Donald O. Pederson Award in Solid-State Circuits. For nearly a century, the IEEE has paid tribute to technical professionals whose exceptional achievements and outstanding efforts have made a lasting impact on technology and society. He was named a Fellow of the IEEE in 1989.

Copeland was presented with the prestigious award on February 1, 2016 at the International Solid-State Circuits Conference in San Francisco. While accepting the award, he reflected back on his time in the Faculty of Engineering and Design.

“This award recognizes Carleton’s leadership in engineering research and innovation,” noted Copeland. “I appreciate the acknowledgement of my hard work and that of Carleton graduate students, whose research helped Nortel establish itself early on as a dominant company in the telecommunications market.”

Dr. Copeland is missed by me and the many colleagues and friends in the Faculty of Engineering and Design at Carleton as well as hundreds of former students. A scholarship was recently established in Dr. Copeland’s name to support outstanding Electronics students. To make a contribution to the fund, please visit futurefunder.ca or contact Corrie Hobin, Assistant Director of Faculty Advancement, Engineering and Design at corrie.hobin@carleton.ca for more information.

How SoC Design is Driving Constraints Management and Verification

There were a number of announcements at DAC 2016 in Austin concerning SDC timing constraints verification and management.  Real Intent announced the newest release of Meridian Constraints for sign-off of SoC designs. It features new and unique functional analysis, data-driven debug, and support for distributed design development.

In this blog, I want to cover the drivers for a new kind of Constraints verification tool.

Constraints Management today is clearly different from the pre-SOC and pre-IP eras. The design process is now truly distributed with much legacy and third-party IP in any new SOC design. This implies that the SDC creation process must go through the three steps of (a) aggregation from the component SDCs to an overall SoC-level SDC, (b) refinement of the SoC-level SDC, and (c) dis-aggregation of the SoC-level SDC into SDCs for the synthesis partitions. The key point here being that the synthesis-partition boundaries need not align with the logical boundaries of the component IPs.

In the pre-SOC and pre-IP era, SDC was created for the monolithic design just prior to synthesis followed by dis-aggregation (budgeting) for the synthesis partitions. It is a benefit that the component IP comes with the associated SDC, but it also means that the SDC management software must be able to digest the component SDCs and create a consistent monolithic SoC-level SDC, i.e. component SDC promotion to the SOC top-level along with SDC consistency checking becomes first-order requirements in an SDC management tool. This has been borne out in surveys we have done with designers, which reveal a 30% pain-point number for consistency checking.

SDC used to be needed first for synthesis followed by static timing analysis (STA), meaning that it was needed late in the design process. In the SoC era, sign-off activity occurs at the RTL level before synthesis partitions are decided. As an important example, RTL must be signed off for clock-domain crossing (CDC) checks before synthesis. Similarly, functional timing exceptions and Reset schemes must be signed-off in RTL before synthesis and STA. These sign-off items require a detailed clocking spec for the sign-off to be meaningful and robust. Not every single SDC detail required for synthesis and STA need to be present at this stage, but the SDC must be detailed enough for CDC sign-off to be reliable. In the SOC and IP-integration era, SDC is needed first for RTL sign-off followed by synthesis and then STA.

Missing and incorrect clock specs are important issues faced in the RTL sign-off process. Usually these gaps can be filled by an analysis of the design and providing the user with templates of SDC commands to be added to the existing constraints. This is borne out in our survey of designers in which the combination of constraints checking, constraints creation and exception verification stands out as a major overhead.

Depending on design methodology, it is true that many exceptions may be “timing intent”, i.e. static configuration registers, resets, etc.  These are not the types of exceptions that can result in silicon failures.  The 20-30% of structural failures cost 100% of the time and money for a re-spin, and it’s important to have a methodology that can validate them completely.  This requires not only a structural analysis of hardware control structures for multi-cycle paths, but also a complementary formal methodology to find any corner cases.  In addition, the ability to configure your exception validation via assertions is crucial to having a complete understanding of your design operation and assumptions before taping out.

If we look at sign-off from the perspective of CDC verification, some tool vendors suggest that the CDC setup process is all about getting clean SDC at RTL level. Getting clock information right is a first step in CDC methodology but it’s just the first step. For a CDC tool to be noise free and waiver free, it should be configurable so it can understand and adapt to various CDC design styles/methodologies used by different design teams across the industry. Also SDC itself is limited because its written for timing intent only, so SDC has no information about what resets signals are in the design.

Meridian Constraints from Real Intent meets the needs of design teams to create, manage, and verify all of their SDC timing constraints. It also ensures that constraints completely cover the design, correctly match the functional and timing goals, and are consistent between different blocks and levels in the design. Having correct and complete constraints and associated clock definitions ensures timing goals are met. Leveraging functional analysis capability with industry-leading formal analysis technology in Meridian Constraints gives users maximum confidence in the correctness of their exceptions, minimizing the risk of a re-spin due to bad exceptions that cause incorrect circuit operation.

This article was based on contributions by Pranav Ashar, CTO, Vikas Sachdeva, senior technical marketing manager, and Daryl Kowalski, senior manager of product engineering at Real Intent.

DAC Preview: 6 Tech. Presentations, Panel on Verification Cost, and the BEST Parties!

Real Intent is bringing its advanced Ascent and Meridian technology, EDA expertise and espresso energy to the 53rd Design Automation Conference (DAC) in Austin, Texas, June 5-9, 2016. Before I mention the BEST DAC parties, Real Intent invites attendees to Booth #527 to:

  • Learn the latest information about Real Intent’s Ascent family of tools for the fastest static RTL verification prior to synthesis and simulation, and its Meridian tools that enable CDC and SDC sign-off at the RTL and gate-level.
  • View technical presentations to get up to speed on Real Intent’s latest advancements, proven on giga-gate SoC and FPGA designs. Click here to make an appointment for one of our private suite presentations:
    • How to Accelerate Your RTL Sign-off
    • Ascent Lint with New Visualization and VHDL 2008
    • Meridian CDC with New Analysis and Data-driven Flow
    • Ascent XV with Advanced Gate-level Pessimism Analysis
    • Case Studies in Physical CDC Analysis for Gate-Level Sign-off
    • New Next-Generation Constraints Exception Verification
  • Complete a quick verification survey to be entered into drawings for a cool Roku 4 streaming player and an Amazon Echo wireless speaker and voice commander.
  • Espresso Yourself and enjoy a high-speed coffee from our DeLonghi Magnifica super-automatic coffee machine, to celebrate faster verification and design.
  • Visit Real Intent and OpenText (Booth #638), Real Intent’s “Espresso Yourself” partner at DAC; get a ticket stamped by both companies to enter drawings to win $100 Amazon Gift Cards.
  • Receive a rose as a sweet thank-you gift.

Real Intent also invites attendees to view What is the Real Cost of Verification — a stimulating panel on Thursday, June 9, from 3:30-4:30 p.m. in room 18AB. Moderated by Kelly Larson of Paradigm Works, panelists Harry Foster of Mentor Graphics Corp., Pranav Ashar of Real Intent, Inc., Raviv Gal of IBM Research, and Subhasish Mitra of Stanford University will discuss what design cost really includes. They also will explore how to measure and improve verification coverage, reduce rework, and improve the chances of first-time silicon success.

BEST DAC PARTIES

Sunday:

Kick-off your DAC with the Welcome Reception, 5:30pm – 7:00pm, 4th floor foyer of the convention center.  Just before, from 5;00pm – 5:30pm is the Gary Smith EDA at the ESD Alliance Kickoff in Ballroom D.

Monday:

HOT Party, Speakeasy, 412 Congress Ave., 7:30 pm to 11:30 pm

Join Heart of Technology and their sponsors at the swankiest party at DAC. They’ll be pouring the giggle water and serving the eats, Al Capone style. Entertainment will be provided by Killer Tofu, the 1990s band playing Green Day, TLC, Grunge and other music you crave. Once again, we are supporting CASA of Travis County with this fundraiser. It’s going to be the bees knees, man! So get your rags together and join us on June 6 at the Speakeasy, voted Austin’s “best swanky” and “best place to party.”  Free to get-in, donations accepted.  Tickets here: HOT Party at DAC 2016

Tuesday:

The Denali Party By Cadence, Tuesday, 8:00pm to 12:30am, Maggie Mae’s, 323 E 6th Street. You need to pre-register (do it now) and you must pick up your wristband at the Cadence booth #107 before noon on Tuesday, or your reservation will be given to another guest.

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Stars of IP 2016, 8:00 pm to 1:00 am, Revival Public House, 340 E 2nd Street
(right across the street from the Austin Convention Center), ticket required.

This is a private party organized by IPextreme and their IP partners and friends. Visit one of the co-hosts below on the DAC Exhibit Floor to inquire about spare tickets.

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Mon., Tues., Wed., Thu.: Don’t forget the daily receptions, 6:00pm to 7:00pm, (5:30pm on Thu.) in the Trinity Street Foyer of the convention center.

See you at the show!

The Switch from Atrenta to Real Intent for CDC, Lint, and X-prop

John Cooley’s Deepchip.com web-site likes to publish end-user experience with various EDA tools.  On May 6, he published a posting on why a designer switched from Atrenta SpyGlass to Real Intent for CDC, Lint, and X-propagation analysis.  His report details the reasons for converting to our best-in-class tool suite.

Here is the first part of the posting:

We had been using SpyGlass from Atrenta, and it worked OK for us, but we
were told by our local Real Intent sales guy that “there would be fewer
iterations for Lint, easier setup for CDC, lower-noise reporting, and
faster runtimes” — if only we evaled his tools.

REAL INTENT MERIDIAN CDC VS. ATRENTA SPYGLASS CDC

I spent one work week (5 days) evaluating Meridian CDC. We used different
designs to evaluate this tool. The first was 850K gate design that had
3 asynchronous clock domains. For the analysis setup, Meridian CDC
automatically detected all the clock/reset candidates correctly at block-
level as well as the top-level. No additions were needed for the setup
file, while our Spyglass run did require manual editing of the setup.
The Meridian runtime for this block was ~5 minutes.

The second design was 4 million gates and had 5 asynchronous clock domains.
Again the automatic clock/reset detection worked as expected. The runtime
was ~15 minutes.

Read the rest of the report on CDC, lint and X-propagation here.

Have you switched EDA tools recently?  How was that experience?

May 17 Event: More than Moore – Enabling the Power of System Scaling

More than Moore – Enabling the Power of System Scaling:
An Open Discussion About Design and Manufacturing Challenges

Join the ESD Alliance on the evening of May 17th at 6PM when we will be hosting an open dialogue about system scaling solutions and what it will take to propel them into the mainstream for semiconductor design and manufacturing. Although various system scaling technologies (such as interposer-based designs, using die-level IP blocks, like HBM) are already in use today, they have not yet crossed into the mainstream.

MultiChip Module

System scaling offers an excellent alternative path to pursuing Moore’s Law by moving the integration focus from the transistor to the integration of several heterogeneous pre-fabricated and proven devices, in the form of die-level IP, into an advanced IC package. Although new sub- 10nm process technologies continue to drive Moore’s Law, development cost and times at these advanced nodes are beyond the reach of much of the mainstream market.

It will take collaboration and cooperation between modeling, design, analysis/verification, manufacturing and test in order to unlock the potential of these new integration solutions. The objective for the meeting is to have an open discussion to identify the highest priority issues that should be jointly worked on to streamline the path to widespread adoption. The ESD Alliance is in the process of forming a working group representing both manufacturing and design to work on practical solutions and is seeking community input on direction and priorities.

This is an open event and we encourage anyone who is involved with or interested in system scaling from either the design or manufacturing perspective to attend. Please join us at 6 pm for networking, food and beverages prior to the open discussion forum, starting at 6:30.

Register Now!
Register Now!
There is no charge for this event.
Participants:
Bob Smith, Executive Director, ESD Alliance
Herb Reiter
, President, eda2asic Consulting, Inc.
Event Details:
Date: Tuesday, May 17 th , 2016
Time: 6:00 PM – 8:00 PM
6:00 PM – 6:30 PM – Registration and networking
6:30 PM – 7:30 PM – Presentations
7:30 PM – 8:00 PM – Discussion
Location: ESD Alliance (SEMI)
3081 Zanker Rd.
San Jose, CA 95134

7 Design Faults Leading to Clock and Data Glitches

Recently I came upon an article by Ankush Sethi of Freescale on the importance of avoiding bad design practices that lead to glitches in clocks which result in asynchronous behavior. He points out:

It is very important to make digital designs free of any clock or data glitches to ensure correct functioning. There are many cases where such issues have caused functional failure, or increased design time through incurring extra debug effort. Hence, it is very important for a designer to take care of such issues at the earliest stages of design once flagged by a tool or gate-level synthesis.

Here is his introduction followed by an iframe of the article from EDN magazine.

With the increasing complexity of SoCs, multiple and independent clocks are essential in the design. The design specifications require system level muxing of some of these clocks before they are sent to actual IP. Also, to save power, clock gating cells are inserted in clock paths. While implementing these muxing and gating cells, a designer tends to make mistakes that can lead to glitches. A glitch on a clock signal exposes a chip (or a section of a chip) to asynchronous behavior. A glitch-prone clock signal driving a flip-flop, memory, or latch may result in incorrect, unstable data. This paper discusses structural faults that can lead to glitches in clocks. Also, some bad design practices that lead to glitches in data are discussed. Read the rest of 7 Design Faults Leading to Clock and Data Glitches

DVClub Silicon Valley: “Using UVM Virtual Sequencers & Virtual Sequences”, Wed. Apr. 27

Please join Silicon Valley verification and design engineers on April 27, 2016 at Dave and Buster’s in Milpitas for a catered lunch, networking, and presentation by Cliff Cummings.  This is a no charge event.

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 Agenda:

11:30am: Doors Open / Networking

12:00pm: Lunch / Presentation

1:00pm: Networking

“Using UVM Virtual Sequencers & Virtual Sequences”

What are virtual sequencers and virtualssequences and when should they be used? Tests that require coordinated generation of stimulus using multiple driving agents benefit from using virtual sequences. This presentation will clarify important concepts and usage techniques related to virtual sequencers and virtual sequences that are not well documented in existing UVM reference materials. This presentation will also detail the m_sequencer and p_sequencer handles and the macros and methods that are used with these handles. The objective of this presentation is to simplify the understanding of virtual sequencers, virtual sequences and how they work.

Cliff Cummings is President of Sunburst Design, Inc., a company that specializes in world-class SystemVerilog, Synthesis and UVM Verification training.Cliff has presented hundreds of SystemVerilog seminars and training classes and has been a featured speaker at multiple world-wide SystemVerilog and Assertion Based Verification seminars. Cliff has been an active participant on every IEEE Verilog and SystemVerilog committee, and has presented more than 50 papers on Verilog & SystemVerilog related design, synthesis, and OVM/UVM verification techniques, including more than 20 that were voted “Best Paper.” Cliff holds a BSEE from Brigham Young University and an MSEE from Oregon State University.

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Verification Coffee Break – Where are We Going?

Pranav Ashar, CTO at Real Intent was interviewed in April by SemIsrael, Israel’s leading semiconductor design and development portal, on the latest trends in the world of verification. Below, I have embedded video clips that cover each of the five questions he addressed. You can watch the entire video here.

Q1. What is the current trend driving verification?

Q2. How are designers meeting these challenges?

 Q3. What static verification solutions are needed?

Q4. What about debug?

Q5. What’s next?

Q6. What is the importance of the Israeli market to Real Intent?

How Physical Implementation Can Break Your Clock-Domain Crossing Logic

At DVCon’16, Mark Litterick presented a paper and presentation on “Full Flow Clock Domain Crossing – From Source to Si.”   Here is the abstract for the paper:

Functional verification of clock domain crossing (CDC) signals is normally concluded on a register-transfer level (RTL) representation of the design. However, physical design implementation during the back-end pre-silicon stages of the flow, which turns the RTL into an optimized gate-level representation, can interfere with synchronizer operation or compromise the effectiveness of the synchronizers by eroding the mean time between failures (MTBF). This paper aims to enhance cross-discipline awareness by providing a comprehensive explanation of the problems that can arise in the physical implementation stages including a detailed analysis of timing intent for common synchronizer circuits.

Mark works for Verilab as senior verification consultant and holds the position of fellow. He is based in Munich, Germany.  To see more of Mark’s technical papers, check out his profile page on the Verilab web-site.

Even though, you may have signed-off for CDC at RTL, logic synthesis, design-for-test and low-power optimization tools can break CDC at the gate-level, the physical implementation stage of design. Real Intent’s Meridian products provide clock-domain crossing verification and sign-off.  Our most recent offering is Meridian Physical CDC and provides sign-off at the netlist level of the design.  It uses a mix of structural and formal methods to identify  glitching and other errors that break the correct registration of signals crossing clock domains.

At this link are the slides for Mark’s presentation.  I have reproduced one of the them for you to outline the specific issues that can compromise CDC at the gate-level .

Mark-slide

At this link is the technical paper that discusses the issue in detail and the pitfalls for different synchronizer approaches. It is worth looking at.

In his conclusion, Mark states:

The  main  advantage  of  running  CDC  analysis  on  the final  netlist  (as  well  as  the  RTL  sign-off  stage)  is  to  pick  up  additional  structural  artifacts  that  were introduced  during  the  back-end  synthesis  stages  such  as  additional  logic  on  CDC  signal  paths  that  might result in glitches, and badly constrained clock-tree synthesis which could for example destroy an intended derived  clock  structure.  The  tools  use  the  same  fundamental  clock  domain  and  synchronizer  protocol descriptions as the RTL phase and can therefore assess if some high-level intent has been compromised.

His last word is:

Finally, we would recommend a methodology which involves an explicit dedicated  CDC and synchronizer review as part of the final pre-silicon sign-off criteria prior to tape-out.

Physical implementation of RTL designs can break the logic for CDC of signals.  A gate-level sign-off for CDC is necessary for modern SoCs or chip failures will be occur in production parts.

Informal, Unformal, or Appformal? …and new FormalWorld.org

Around the Design and Verification Conference in San Jose at the beginning of the March, a lot of activity was happening in the online world in preparation for the big meetup of the verification community.

First, the DeepChip.com web-site published a set of five (5) articles that surveyed the world of formal verification in EDA, written by Jim Hogan, of Vista Ventures, a Silicon Valley investment firm.  Jim is currently on the Board of OneSpin, a formal tools company.  Knowing Jim, he did his homework before getting involved with them.  If you read the articles, which total 12,000 words, you will have to agree with me there is a lot of great content here.  If a technical writer charged for producing this, you would be looking at a bill close to $20,000.

These days you have to two general ways to verify the functionality of your RTL with formal.  You either write your own properties and then feed them and the RTL to a formal property verifier (FPV) tool, OR you have an application-focused formal tool  automatically read and apply properties to your design.

In the early days of Real Intent we had our own FPV tool.  However, by the late 2000’s we realized that designers needed specific solutions to verification problems.  And so instead of attacking the general verification market, we focused on clock-domain crossing verification, and automatic code-checks for common RTL problems with FSMs, dead-code, etc.  This lead to our existing suite of Meridian and Ascent products which cover five (5) different categories.

In the fourth article by Jim, “16 Formal Apps that make Formal easy for us non-Formal engineers“, Jim uses the “apps” moniker to identify this category.  Our CTO, Pranav Ashar, takes exception to this term.  In his view, “app” has been subverted to convey a pejorative sense as in “It is just an app!”  It has become something to download to your phone to use without a second thought, and with a corresponding low value.

Our Meridian clock-domain crossing sign-off tool fits into the CDC app category, but there is a substantial amount of software technology under-the-hood to make it effective for a wide-range of designs.  If CDC is an “app” so is static timing analysis (STA). But nobody calls STA an “app”!

Perhaps this new category of problem-focused formal applications, which are easy to use, need a different label.  Since these new formal tools are targeted to ordinary engineers and not PhD’s,  perhaps we could call these solutions “informal”, “unformal” or even “appformal”.

What do you think?

Second, a new web-site called FormalWorld.org has just been launched. It is an open and free community, and anyone interested in Formal Verification is invited to post relevant and useful information, or write a blog.  It is intended to make it easy to explore and learn about formal, as well as to share experience and research with others.  It is sponsored by OneSpin but has pointers and content for all the formal verification suppliers, including Real Intent. OneSpin “will take a hands-off role in its management.”

The site is managed by Jan Kuster, an independent consultant. Contact Jan Kuster with content suggestions or ideas at ContactUs@FormalWorld.org.

I looked around the site and I guarantee you will see something that will interest you.

I did read the blog post by Elchanan Rappaport of Gila Logic.  Titled “Formal Evaluations, or the Fine Art of Shooting Yourself in the Foot” it gives a real world experience of introducing a FPV tool to a company and what trouble can arise.  A great balance to Jim’s articles, I recommend everyone considering a FPV tool to read it and learn from other’s experience.