Innovating the Intelligence of Formal Techniques for Automatic Design Verification
Blog Archive
February 2012
2/15/2012: Avoiding the Titanic-Sized Iceberg of Downton Abbey
January 2012
1/24/2012: A Meaningful Present for the New Year
August 2011
8/02/2011: A Quick History of Clock Domain Crossing (CDC) Verification
July 2011
7/26/2011: Hardware-Assisted Verification and the Animal Kingdom
7/13/2011: Advanced Sign-off…It’s Trending!
May 2011
5/24/2011: Learn about Advanced Sign-off Verification at DAC 2011
5/16/2011: Getting A Jump On DAC
5/09/2011: Livin’ on a Prayer
5/02/2011: The Journey to CDC Sign-Off
April 2011
4/25/2011: Getting You Closer to Verification Closure
4/11/2011: X-verification: Conquering the “Unknown”
4/05/2011: Learn About the Latest Advances in Verification Sign-off!
March 2011
3/21/2011: Business Not as Usual
3/15/2011: The Evolution of Sign-off
3/07/2011: Real People, Real Discussion – Real Intent at DVCon
February 2011
2/28/2011: The Ascent of Ascent Lint (v1.4 is here!)
2/21/2011: Foundation for Success
2/08/2011: Fairs to Remember
January 2011
1/31/2011: EDA Innovation
1/24/2011: Top 3 Reasons Why Designers Switch to Meridian CDC from Real Intent
1/17/2011: Hot Topics, Hot Food, and Hot Prize
1/10/2011: Satisfaction EDA Style!
1/03/2011: The King is Dead. Long Live the King!
December 2010
12/20/2010: Hardware Emulation for Lowering Production Testing Costs
12/03/2010: What do you need to know for effective CDC Analysis?
November 2010
11/12/2010: The SoC Verification Gap
11/05/2010: Building Relationships Between EDA and Semiconductor Ventures
October 2010
10/29/2010: Thoughts on Assertion Based Verification (ABV)
10/25/2010: Who is the master who is the slave?
10/08/2010: Economics of Verification
10/01/2010: Hardware-Assisted Verification Tackles Verification Bottleneck
September 2010
9/24/2010: Excitement in Electronics
9/17/2010: Achieving Six Sigma Quality for IC Design
9/03/2010: A Look at Transaction-Based Modeling
August 2010
8/20/2010: The 10 Year Retooling Cycle
July 2010
7/30/2010: Hardware-Assisted Verification Usage Survey of DAC Attendees
7/23/2010: Leadership with Authenticity
7/16/2010: Clock Domain Verification Challenges: How Real Intent is Solving Them
7/09/2010: Building Strong Foundations
7/02/2010: Celebrating Freedom from Verification
June 2010
6/25/2010: My DAC Journey: Past, Present and Future
6/18/2010: Verifying Today’s Large Chips
6/11/2010: You Got Questions, We Got Answers
6/04/2010: Will 70 Remain the Verification Number?
May 2010
5/28/2010: A Model for Justifying More EDA Tools
5/21/2010: Mind the Verification Gap
5/14/2010: ChipEx 2010: a Hot Show under the Hot Sun
5/07/2010: We Sell Canaries
April 2010
4/30/2010: Celebrating 10 Years of Emulation Leadership
4/23/2010: Imagining Verification Success
4/16/2010: Do you have the next generation verification flow?
4/09/2010: A Bug’s Eye View under the Rug of SNUG
4/02/2010: Globetrotting 2010
March 2010
3/26/2010: Is Your CDC Tool of Sign-Off Quality?
3/19/2010: DATE 2010 – There Was a Chill in the Air
3/12/2010: Drowning in a Sea of Information
3/05/2010: DVCon 2010: Awesomely on Target for Verification
February 2010
2/26/2010: Verifying CDC Issues in the Presence of Clocks with Dynamically Changing Frequencies
2/19/2010: Fostering Innovation
2/12/2010: CDC (Clock Domain Crossing) Analysis – Is this a misnomer?
2/05/2010: EDSFair – A Successful Show to Start 2010
January 2010
1/29/2010: Ascent Is Much More Than a Bug Hunter
1/22/2010: Ascent Lint Steps up to Next Generation Challenges
1/15/2010: Google and Real Intent, 1st Degree LinkedIn
1/08/2010: Verification Challenges Require Surgical Precision
1/07/2010: Introducing Real Talk!

Hardware-Assisted Verification and the Animal Kingdom

Lauro Rizzatti   Lauro Rizzatti
   General Manager of EVE-USA

A senior executive of one of the big three EDA vendors was once quoted as saying:  “An emulator you used four years ago, you can use as a bookend, but not much else.  Or, you can throw it over the side of a boat and use it to grow coral.”

While we’ve chuckled over this comment for years, we think a better analogy comes from another part of the animal kingdom and it goes something like this:  Traditional hardware emulators are a lot like the dinosaurs that roamed the earth for 160 million years.  Both are now extinct, the latter wiped out at the end of the Mesozoic Era.  The former, wiped out by hardware-assisted verification platforms designed and implemented with the largest commercial FPGAs that are as fast and sleek as a Gazelle.

Dinosaurs were dominant terrestrial vertebrates, a term that sounds slow, plodding and ponderous, not at all unlike the description of early hardware emulators.

At their introduction in the 1980s, emulators were considered revolutionary and a bold feat of engineering marvel.  The high cost of ownership, however, limited adoption to big companies with large budgets and complex design problems.  Further, a traditional emulator’s maximum speed was about one megahertz (MHz), slow even then.  They were also criticized for being difficult to set up, wasting time and resources.  A common refrain in those early days was the excessive time to emulation.

Dinosaurs are known to have laid eggs.  Hmmm.

As we compare the latest generation of hardware emulation systems to the impressive gazelle, it’s easy to understand why they are changing designers’ perception of this market segment.  They perform at significantly faster speeds, are notably dexterous in their design verification deployment, and drastically more cost effective.

Gazelles are reputed to be swift animals.  In fact, some are able to maintain speeds as high as 50 miles per hour for extended periods of time.  Today’s emulation systems are equally swift –– some clock in at 10 megahertz (MHz) on a 40-million gate design.

These new functional verification engines have a small footprint and are light weight, saving space, power and infrastructure costs, and execute at speeds of several megahertz even in transaction-based co-emulation.  Their debugging capabilities are similar to those of the beloved HDL simulator.  Even more attractive is their pricing –– they sell for a fraction of the cost of older generations of emulators.  They can be used by the embedded software team and hardware designers for hardware/software co-verification, and increasingly are used as a solution to an event-based simulator’s runtime problems.

The gazelle is appreciated for being both nimble and graceful, and does not lay eggs.

Experts tell us we can learn much from the Animal Kingdom.  We’ve learned enough to be able to compare and contrast the characteristics of chip verification tools to two venerated animals.  As we’ve shown, traditional emulators have gone the way of the Dinosaur while today’s fast emulation systems are emulating the characteristics of a Gazelle.

Jul 26, 2011

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