Blog Archive
May 2012
5/08/2012: Gabe on EDA: Real Intent Helps Designers Verify Intent
5/07/2012: EDACafe: A Page is Turned
5/07/2012: Press Release: Graham Bell Joins Real Intent to Promote Early Functional Verification & Advanced Sign-Off Circuit Design Software
March 2012
3/21/2012: Press Release: Real Intent Demos EDA Solutions for Early Functional Verification & Advanced Sign-off at Synopsys Users Group (SNUG)
3/20/2012: Article: Blindsided by a glitch
3/16/2012: Gabe on EDA: Real Intent and the X Factor
3/10/2012: DVCon Video Interview: “Product Update and New High-capacity ‘X’ Verification Solution”
3/01/2012: Article: X-Propagation Woes: Masking Bugs at RTL and Unnecessary Debug at the Netlist
February 2012
2/28/2012: Press Release: Real Intent Joins Cadence Connections Program; Real Intent’s Advanced Sign-Off Verification Capabilities Added to Leading EDA Flow
2/15/2012: Real Intent Improves Lint Coverage and Usability
2/15/2012: Avoiding the Titanic-Sized Iceberg of Downton Abbey
2/08/2012: Gabe on EDA: Real Intent Meridian CDC
2/08/2012: Press Release: At DVCon, Real Intent Verification Experts Present on Resolving X-Propagation Bugs; Demos Focus on CDC and RTL Debugging Innovations
January 2012
1/24/2012: A Meaningful Present for the New Year
1/11/2012: Press Release: Real Intent Solidifies Leadership in Clock Domain Crossing
August 2011
8/02/2011: A Quick History of Clock Domain Crossing (CDC) Verification
July 2011
7/26/2011: Hardware-Assisted Verification and the Animal Kingdom
7/13/2011: Advanced Sign-off…It’s Trending!
May 2011
5/24/2011: Learn about Advanced Sign-off Verification at DAC 2011
5/16/2011: Getting A Jump On DAC
5/09/2011: Livin’ on a Prayer
5/02/2011: The Journey to CDC Sign-Off
April 2011
4/25/2011: Getting You Closer to Verification Closure
4/11/2011: X-verification: Conquering the “Unknown”
4/05/2011: Learn About the Latest Advances in Verification Sign-off!
March 2011
3/21/2011: Business Not as Usual
3/15/2011: The Evolution of Sign-off
3/07/2011: Real People, Real Discussion – Real Intent at DVCon
February 2011
2/28/2011: The Ascent of Ascent Lint (v1.4 is here!)
2/21/2011: Foundation for Success
2/08/2011: Fairs to Remember
January 2011
1/31/2011: EDA Innovation
1/24/2011: Top 3 Reasons Why Designers Switch to Meridian CDC from Real Intent
1/17/2011: Hot Topics, Hot Food, and Hot Prize
1/10/2011: Satisfaction EDA Style!
1/03/2011: The King is Dead. Long Live the King!
December 2010
12/20/2010: Hardware Emulation for Lowering Production Testing Costs
12/03/2010: What do you need to know for effective CDC Analysis?
November 2010
11/12/2010: The SoC Verification Gap
11/05/2010: Building Relationships Between EDA and Semiconductor Ventures
October 2010
10/29/2010: Thoughts on Assertion Based Verification (ABV)
10/25/2010: Who is the master who is the slave?
10/08/2010: Economics of Verification
10/01/2010: Hardware-Assisted Verification Tackles Verification Bottleneck
September 2010
9/24/2010: Excitement in Electronics
9/17/2010: Achieving Six Sigma Quality for IC Design
9/03/2010: A Look at Transaction-Based Modeling
August 2010
8/20/2010: The 10 Year Retooling Cycle
July 2010
7/30/2010: Hardware-Assisted Verification Usage Survey of DAC Attendees
7/23/2010: Leadership with Authenticity
7/16/2010: Clock Domain Verification Challenges: How Real Intent is Solving Them
7/09/2010: Building Strong Foundations
7/02/2010: Celebrating Freedom from Verification
June 2010
6/25/2010: My DAC Journey: Past, Present and Future
6/18/2010: Verifying Today’s Large Chips
6/11/2010: You Got Questions, We Got Answers
6/04/2010: Will 70 Remain the Verification Number?
May 2010
5/28/2010: A Model for Justifying More EDA Tools
5/21/2010: Mind the Verification Gap
5/14/2010: ChipEx 2010: a Hot Show under the Hot Sun
5/07/2010: We Sell Canaries
April 2010
4/30/2010: Celebrating 10 Years of Emulation Leadership
4/23/2010: Imagining Verification Success
4/16/2010: Do you have the next generation verification flow?
4/09/2010: A Bug’s Eye View under the Rug of SNUG
4/02/2010: Globetrotting 2010
March 2010
3/26/2010: Is Your CDC Tool of Sign-Off Quality?
3/19/2010: DATE 2010 – There Was a Chill in the Air
3/12/2010: Drowning in a Sea of Information
3/05/2010: DVCon 2010: Awesomely on Target for Verification
February 2010
2/26/2010: Verifying CDC Issues in the Presence of Clocks with Dynamically Changing Frequencies
2/19/2010: Fostering Innovation
2/12/2010: CDC (Clock Domain Crossing) Analysis – Is this a misnomer?
2/05/2010: EDSFair – A Successful Show to Start 2010
January 2010
1/29/2010: Ascent Is Much More Than a Bug Hunter
1/22/2010: Ascent Lint Steps up to Next Generation Challenges
1/15/2010: Google and Real Intent, 1st Degree LinkedIn
1/08/2010: Verification Challenges Require Surgical Precision
1/07/2010: Introducing Real Talk!

Real People, Real Discussion – Real Intent at DVCon

Carol Hallett   Carol Hallett
   VP of World Wide Sales for Real Intent

There are many trade shows & conferences for an EDA company to consider each year, and the decision may not be easy for small companies, as it involves tradeoffs on where the company should spend its resources. However, of all the options, DVCon has consistently proven to be of great value for Real Intent.

Larger trade shows like DAC offer an opportunity to reach more people, but with many different types of engineers in attendance, looking for everything from ESL to full custom design, the small guys can get lost in the shuffle.  It can also be hard to get the approval to drive a panel, or hold a technical session. Therefore, small companies must work harder to get noticed among so many vendors, and most importantly, to reach the right audience for their products.

That’s why the smaller and more focused shows, like DVCon, offer a special opportunity for companies like Real Intent.  We know that Design and Verification Engineers will be attending this show.  We know that they are coming for the technical presentations.  We know that the exhibit floor is a place they come to take a break from the brain dump they are getting upstairs.  And we know that they will do a walk-through, stop by to hear about our products, and have a glass of wine and enjoy the appetizers that are being distributed by the smiling servers.  One of the attendees mentioned to me that this was his favorite part of the show because it felt like old home week…we are all colleagues in this space, and you can feel the closeness in the room while we discuss the changing verification landscape.  This has value!

This is exactly what we experience every year at DVCon. And, with an improved economy, this year at DVCon the attendance seemed to be very robust, with a lot of people coming from faraway places such as East Coast, Canada, Korea, and India. Through conversations, we learned that many people were faithful readers of this blog; they followed our news releases and press coverage and came to talk to us specifically to find out more. That is the value of having such a focused event like DVCon.

Another thing we greatly value at DVCon is the opportunity to learn from the Design and Verifiation Engineers that attend. To that end, we conducted a survey to learn what concerns and attitudes they have about various verification topics. And, we selected one lucky survey respondent to win a special prize (more on that later)! Among the questions on the survey, several yielded some interesting statistics that I will share with you.

One interesting question asked whether respondents had ever had a bug slip through to silicon due to a CDC problem. The majority – 60% – replied “Yes”. With the number of clock domains in SoCs going up, this number will probably increase unless designers adopt a comprehensive CDC verification solution and make it a sign-off criterion.

Speaking of that, we also asked respondents whether they consider CDC Verification a sign-off criterion today. Two-thirds replied “Yes”, indicating just how serious they consider CDC as an emerging verification issue. Clearly, simulation and timing verification alone can no longer pass as the only technologies required for verification sign-off.

Finally, we took the opportunity to ask about an emerging issue: bugs that slip through to silicon due to differing interpretation of X-Propagation by simulation and synthesis. This is an issue that has always been there, but with the rapid growth in SoC size and complexity, it is becoming a first-order concern for Design and Verification Engineers. When we asked about this, 40% of respondents told us that they are “Very Concerned” about X-Propagation bugs, while 45% said they were “Moderately Concerned”. Only 15% were not concerned. This is obviously an area in need of a verification solution and will get much more attention going forward.

With such informed attendees and the resulting interesting discussion, it is pretty obvious why we love DVCon: it offers opportunities to not only meet qualified users, and build relationships with people in the industry, but also to have in-depth and intimate conversation with real people having real design & verification challenges and seeking real solutions, and to learn from them!

So – A big thanks to everyone who visited us at DVCon and participated in our survey. Of course, I shouldn’t forget to mention our lucky winner for the drawing of an Amazon Kindle:

Krishnan Venkitakrishnan

Program Manager, Chipset Enablement

Industry Standard Servers

Hewlett-Packard

Congratulations Krishnan! We look forward to seeing you all next year at DVCon 2012!

Mar 7, 2011

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