There are many trade shows & conferences for an EDA company to consider each year, and the decision may not be easy for small companies, as it involves tradeoffs on where the company should spend its resources. However, of all the options, DVCon has consistently proven to be of great value for Real Intent.
Larger trade shows like DAC offer an opportunity to reach more people, but with many different types of engineers in attendance, looking for everything from ESL to full custom design, the small guys can get lost in the shuffle. It can also be hard to get the approval to drive a panel, or hold a technical session. Therefore, small companies must work harder to get noticed among so many vendors, and most importantly, to reach the right audience for their products.
That’s why the smaller and more focused shows, like DVCon, offer a special opportunity for companies like Real Intent. We know that Design and Verification Engineers will be attending this show. We know that they are coming for the technical presentations. We know that the exhibit floor is a place they come to take a break from the brain dump they are getting upstairs. And we know that they will do a walk-through, stop by to hear about our products, and have a glass of wine and enjoy the appetizers that are being distributed by the smiling servers. One of the attendees mentioned to me that this was his favorite part of the show because it felt like old home week…we are all colleagues in this space, and you can feel the closeness in the room while we discuss the changing verification landscape. This has value!
This is exactly what we experience every year at DVCon. And, with an improved economy, this year at DVCon the attendance seemed to be very robust, with a lot of people coming from faraway places such as East Coast, Canada, Korea, and India. Through conversations, we learned that many people were faithful readers of this blog; they followed our news releases and press coverage and came to talk to us specifically to find out more. That is the value of having such a focused event like DVCon.
Another thing we greatly value at DVCon is the opportunity to learn from the Design and Verifiation Engineers that attend. To that end, we conducted a survey to learn what concerns and attitudes they have about various verification topics. And, we selected one lucky survey respondent to win a special prize (more on that later)! Among the questions on the survey, several yielded some interesting statistics that I will share with you.
One interesting question asked whether respondents had ever had a bug slip through to silicon due to a CDC problem. The majority – 60% – replied “Yes”. With the number of clock domains in SoCs going up, this number will probably increase unless designers adopt a comprehensive CDC verification solution and make it a sign-off criterion.
Speaking of that, we also asked respondents whether they consider CDC Verification a sign-off criterion today. Two-thirds replied “Yes”, indicating just how serious they consider CDC as an emerging verification issue. Clearly, simulation and timing verification alone can no longer pass as the only technologies required for verification sign-off.
Finally, we took the opportunity to ask about an emerging issue: bugs that slip through to silicon due to differing interpretation of X-Propagation by simulation and synthesis. This is an issue that has always been there, but with the rapid growth in SoC size and complexity, it is becoming a first-order concern for Design and Verification Engineers. When we asked about this, 40% of respondents told us that they are “Very Concerned” about X-Propagation bugs, while 45% said they were “Moderately Concerned”. Only 15% were not concerned. This is obviously an area in need of a verification solution and will get much more attention going forward.
With such informed attendees and the resulting interesting discussion, it is pretty obvious why we love DVCon: it offers opportunities to not only meet qualified users, and build relationships with people in the industry, but also to have in-depth and intimate conversation with real people having real design & verification challenges and seeking real solutions, and to learn from them!
So – A big thanks to everyone who visited us at DVCon and participated in our survey. Of course, I shouldn’t forget to mention our lucky winner for the drawing of an Amazon Kindle:
Program Manager, Chipset Enablement
Industry Standard Servers
Congratulations Krishnan! We look forward to seeing you all next year at DVCon 2012!