Blog Archive
May 2012
5/08/2012: Gabe on EDA: Real Intent Helps Designers Verify Intent
5/07/2012: EDACafe: A Page is Turned
5/07/2012: Press Release: Graham Bell Joins Real Intent to Promote Early Functional Verification & Advanced Sign-Off Circuit Design Software
March 2012
3/21/2012: Press Release: Real Intent Demos EDA Solutions for Early Functional Verification & Advanced Sign-off at Synopsys Users Group (SNUG)
3/20/2012: Article: Blindsided by a glitch
3/16/2012: Gabe on EDA: Real Intent and the X Factor
3/10/2012: DVCon Video Interview: “Product Update and New High-capacity ‘X’ Verification Solution”
3/01/2012: Article: X-Propagation Woes: Masking Bugs at RTL and Unnecessary Debug at the Netlist
February 2012
2/28/2012: Press Release: Real Intent Joins Cadence Connections Program; Real Intent’s Advanced Sign-Off Verification Capabilities Added to Leading EDA Flow
2/15/2012: Real Intent Improves Lint Coverage and Usability
2/15/2012: Avoiding the Titanic-Sized Iceberg of Downton Abbey
2/08/2012: Gabe on EDA: Real Intent Meridian CDC
2/08/2012: Press Release: At DVCon, Real Intent Verification Experts Present on Resolving X-Propagation Bugs; Demos Focus on CDC and RTL Debugging Innovations
January 2012
1/24/2012: A Meaningful Present for the New Year
1/11/2012: Press Release: Real Intent Solidifies Leadership in Clock Domain Crossing
August 2011
8/02/2011: A Quick History of Clock Domain Crossing (CDC) Verification
July 2011
7/26/2011: Hardware-Assisted Verification and the Animal Kingdom
7/13/2011: Advanced Sign-off…It’s Trending!
May 2011
5/24/2011: Learn about Advanced Sign-off Verification at DAC 2011
5/16/2011: Getting A Jump On DAC
5/09/2011: Livin’ on a Prayer
5/02/2011: The Journey to CDC Sign-Off
April 2011
4/25/2011: Getting You Closer to Verification Closure
4/11/2011: X-verification: Conquering the “Unknown”
4/05/2011: Learn About the Latest Advances in Verification Sign-off!
March 2011
3/21/2011: Business Not as Usual
3/15/2011: The Evolution of Sign-off
3/07/2011: Real People, Real Discussion – Real Intent at DVCon
February 2011
2/28/2011: The Ascent of Ascent Lint (v1.4 is here!)
2/21/2011: Foundation for Success
2/08/2011: Fairs to Remember
January 2011
1/31/2011: EDA Innovation
1/24/2011: Top 3 Reasons Why Designers Switch to Meridian CDC from Real Intent
1/17/2011: Hot Topics, Hot Food, and Hot Prize
1/10/2011: Satisfaction EDA Style!
1/03/2011: The King is Dead. Long Live the King!
December 2010
12/20/2010: Hardware Emulation for Lowering Production Testing Costs
12/03/2010: What do you need to know for effective CDC Analysis?
November 2010
11/12/2010: The SoC Verification Gap
11/05/2010: Building Relationships Between EDA and Semiconductor Ventures
October 2010
10/29/2010: Thoughts on Assertion Based Verification (ABV)
10/25/2010: Who is the master who is the slave?
10/08/2010: Economics of Verification
10/01/2010: Hardware-Assisted Verification Tackles Verification Bottleneck
September 2010
9/24/2010: Excitement in Electronics
9/17/2010: Achieving Six Sigma Quality for IC Design
9/03/2010: A Look at Transaction-Based Modeling
August 2010
8/20/2010: The 10 Year Retooling Cycle
July 2010
7/30/2010: Hardware-Assisted Verification Usage Survey of DAC Attendees
7/23/2010: Leadership with Authenticity
7/16/2010: Clock Domain Verification Challenges: How Real Intent is Solving Them
7/09/2010: Building Strong Foundations
7/02/2010: Celebrating Freedom from Verification
June 2010
6/25/2010: My DAC Journey: Past, Present and Future
6/18/2010: Verifying Today’s Large Chips
6/11/2010: You Got Questions, We Got Answers
6/04/2010: Will 70 Remain the Verification Number?
May 2010
5/28/2010: A Model for Justifying More EDA Tools
5/21/2010: Mind the Verification Gap
5/14/2010: ChipEx 2010: a Hot Show under the Hot Sun
5/07/2010: We Sell Canaries
April 2010
4/30/2010: Celebrating 10 Years of Emulation Leadership
4/23/2010: Imagining Verification Success
4/16/2010: Do you have the next generation verification flow?
4/09/2010: A Bug’s Eye View under the Rug of SNUG
4/02/2010: Globetrotting 2010
March 2010
3/26/2010: Is Your CDC Tool of Sign-Off Quality?
3/19/2010: DATE 2010 – There Was a Chill in the Air
3/12/2010: Drowning in a Sea of Information
3/05/2010: DVCon 2010: Awesomely on Target for Verification
February 2010
2/26/2010: Verifying CDC Issues in the Presence of Clocks with Dynamically Changing Frequencies
2/19/2010: Fostering Innovation
2/12/2010: CDC (Clock Domain Crossing) Analysis – Is this a misnomer?
2/05/2010: EDSFair – A Successful Show to Start 2010
January 2010
1/29/2010: Ascent Is Much More Than a Bug Hunter
1/22/2010: Ascent Lint Steps up to Next Generation Challenges
1/15/2010: Google and Real Intent, 1st Degree LinkedIn
1/08/2010: Verification Challenges Require Surgical Precision
1/07/2010: Introducing Real Talk!

EDA Innovation

Lauro Rizzatti   Lauro Rizzatti
   General Manager of EVE-USA

I recently came across this quote from Robert Noyce:  “Optimism is an essential ingredient for innovation.  How else can the individual welcome change over security, adventure over staying in safe places?” 

Noyce knew a thing or two about innovation and the alchemy to create it.  The “Mayor of Silicon Valley” co-founded Fairchild Semiconductor and Intel, and is credited, along with Jack Kilby, with inventing the integrated circuit.  He had both an impressive career and an impressive grasp on innovation.

Armed with this quote, Bob Noyce as a role model and a bit of innovative thinking, I went looking for innovation in EDA.  I’m happy to report that I found it, starting with many of the recipients of the Phil Kaufman Award.  Kaufman, who died in 1992 while on a business trip in Japan, was a creative and innovative force within the areas of hardware, software, semiconductors, EDA and computer architecture.  He was CEO of Quickturn Design Systems, now part of Cadence, and accelerated the use of emulation.  It’s easy to understand why a prestigious industry award carries his name.

The emulation and verification space is one segment of EDA that creates unlimited opportunities for innovative types.  The founders of my company EVE, for example, boldly redesigned the architecture of a hardware emulation platform and, in my humble opinion, transformed a market segment. 

Real Intent is another good example.  Formal verification is a hard and complicated problem.  That didn’t appear to deter Real Intent’s founders who pressed on and devised an innovative approach that makes the lives of many verification engineers much easier.

Entrepreneurial Rajeev Madhavan concluded in the late 1990s that synthesis needed to be linked with physical design.  He and his innovative team at Magma introduced the first physical synthesis and rocked the industry.  And, with Madhavan still at the helm, Magma is still innovating today.  Now, Oasys Design Systems’ team introduced a new synthesis methodology known as Chip Synthesis, enabling designers to synthesize full chips and not just blocks.  That technology, too, is rocking the industry.

Over in Alameda, Calif., Verific Design Automation has taken the mundane task of developing hardware description language parsers and elaborators and built it into a successful business.  In the meantime, these tools have become the industry’s de facto standard front-end software for just about every imaginable EDA and FPGA company.  This is innovative thinking at its greatest.

Of course, anyone who has been in EDA for a while can point to pockets of tremendous optimism and enthusiasm that resonates throughout the industry.  Who needs security or a safe place when there was a big adventure with an innovative and entrepreneurial big thinker just waiting for you in the Silicon Valley office complex next door?

We’re heading into DVCon later this month and DAC in June where we will see many more examples of creative thinking, enthusiasm and optimism in EDA.  I am looking forward to being wowed.

Jan 31, 2011

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