Real Intent on DeepChip’s Cheesy List for DAC 2017

DeepChip: “My Cheesy Must See List for DAC 2017”

Real Intent on this year’s Cheesy List:

Real Intent Meridian CDC does new transparent hierarchical models for separate CDC analyses at unit-level.  New consistency checks across chip hierarchy.  On 300M gate chip with 103 clock domains, the hierarchical CDC runtime cut by 5X and memory use cut by 4X.  (booth 928)  Ask Vikas Sachdeva.  Freebie: cellphone batteries

NEW! — Real Intent Verix Multimode CDC is a “brand new tool for true multi-mode CDC RTL analysis.”  Single set-up.  All modes in single run, no iterations.  New static intent verification finds non-operational clock modes. Vs. Spyglass or Questa, it saves 3.3x CPU time and 5x engineering time per iteration.  See ESNUG 574 #2. (booth 928)  Ask Vikas Sachdeva.  Freebie: cellphone batteries

Real Intent Ascent XV does X-propagation checks.  Ranks X-sources and X-sensitive nets by failure importance.  Initialization audits. Setup-free X-pessimism analysis at gate-level with only 3X overhead versus 5x-10X from other tools.  Now goes deeper; found a gate-level Xs in a 220M gate design.  Replaces using VCS/Incisive/Questa’s X-safe simulation switches.  Finds minimally correct reset schemes.
(booth 928)  Ask Lisa Piper.  Freebie: cellphone batteries

NEW! — Real Intent Meridian RDC finds reset configurations and complex reset interactions, not covered by existing tools.  Finds reset metastability and glitch problems.  Optimized data models. 200M gate full chip RDC analysis in 9 hrs with ~160 G memory.