High-Level Synthesis: New Driver for RTL Verification

In a recent blog, Does Your Synthesis Code Play Well With Others?,  I explored some of the requirements for verifying the quality of the RTL code generated by high-level synthesis (HLS) tools.  At a minimum, a state-of-the-art lint tool should be used to ensure that there are no issues with the generated code.  Results can be achieved in minutes, if not seconds for generated blocks.

What else can be done to ensure the quality of the generated RTL code?   For functional verification, an autoformal tools, like Real Intent’s Ascent IIV product can be used to ensure that basic operation is correct.   The IIV tools will automatically generate sequences and detect whether incorrect or undesirable behavior can occur.   Here is a quick list of what IIV can catch in the generated code:

  • FSM deadlocks and unreachable states
  • Bus contention and floating busses
  • Full- and Parallel-case pragma violations
  • Array bounds
  • Constant RTL expressions, nets & state vector bits
  • Dead code

dffDesigners are are also concerned about the resettability of their designs and if they power-up into a known good state.  We have seen some interesting results when Real Intent’s Ascent XV tool is applied to RTL blocks generated by HLS.  Besides analyzing X-optimism and X-pessimism, the Ascent XV tool can determine the minimum number of flops that need to have reset lines routed to them.  To save routing resources and reduce power requirements a minimal set of flops should be used.  Running additional lines does not improve the design.

Here are the results for a block that was 130K gates in size:

Number of Flops 17,495
Ascent XV Analysis Time (sec) 20
Unitialized Flops Found 646
Percent Initialized 96%
Redundant Flops Initialization 11,896
Reset Savings 68%

In this example, the Ascent XV tool took 20 seconds to analyze all 17,495 flops and discover that 646 were unitialized and that of the roughly 16,800 other flops, most of these did not need to have reset signals routed to them.   The savings were 68% compared to the unimproved design.  We have seen similar savings on other blocks generated by HLS tools.

HLS is now an important part of the hardware flow, and improves the productivity of designers.  With easy generation of RTL code, designers should expert to use quick static verification tools such as lint, autoformal, and reset analysis to confirm quality and correct operation.  This will save valuable time when designs are given to simulation and gate-level synthesis tools later in the flow.