First generation tools historically evolved as extensions of simple linters and source checkers or by the application of basic formal engines in an attempt to solve the CDC problem. These tools generated voluminous reports and required designers to painfully plow through tens of thousands of less than informative messages for days and weeks to overcome the “signal to noise” problem. Such a methodology is prohibitive for any practical chip-level analysis. Even employing post-analysis filtering of design structures such as FIFOs and handshakes have proven to be a daunting and time-intensive task for designers trying to find real CDC violations.

While there are multiple vendors offering CDC analysis tools, some developed as extensions of lint engines, and newer ones like Real Intent’s Meridian CDC designed from the ground up with a first principles understanding of CDC failure modes, any tool must ultimately provide value as a viable sign-off-quality tool for designers and project managers with easy setup and report-analysis capabilities, comprehensive checking, and practical execution times.

A sign-off quality tool must meet the following criteria:

Easy to setup and use
Comprehensive analysis of all asynchronous crossing issues while being tolerant to design styles
Manageable analysis results and easy exception handling
Practical run time performance with full SoC flow management

A sign-off-quality tool must include easy and true automated setup for CDC, recognition of all metastability control structures, and not be limited to coding styles/structures in order to recognize, for example, FIFO structures. It is imperative for such recognition technology to work equally well at the netlist level in addition to the RT level. With Meridian’s automatic CDC recognition technology, for example, all asynchronous FIFO structures are recognized at both RT and netlist levels.

A sign-off quality tool must be comprehensive in its analysis capability. It would include capability to catch all CDC and asynchronous crossing bugs while being tolerant of design practices. It would also be glitch aware and detect all glitch sources, perform pulse-width verification, perform complete cycle-jitter analysis on clock and data paths, and support free running clock analysis.

Sign-off quality tool must provide for manageable analysis results and exception handling. Any limitations in the structural recognition of asynchronous control leads to in the analysis reports and makes the manual analysis of the report very time consuming. Full SOC analysis should be performed in the order of hours and not days for typical design sizes (5 Million to 40 Million gates). Because of transformations induced by timing-driven synthesis optimizations, and test-driven and power optimization-driven modifications of the clock structures, running at least structural CDC at the netlist level is a must. Running at least structural CDC analysis is becoming ever more important even for the post-layout stages of a design. With Meridian’s technology, these capabilities are all a reality today with low noise due to Meridian’s complete asynchronous-control-structure recognition.

Finally, execution time must be manageable to the point that it can support quick feedback to the designer. Overnight runs are simply not practical for such analysis. Considering the fact that often CDC analysis is performed at the tail-end of the RTL signoff process when schedule pressures are greatest, using basic linters for CDC analysis generally leads to frustration. It is not uncommon for run-times to prevent designers from finishing complete full chip analysis.

So, if your CDC tool does not pass muster in any or all of the above issues as covered in this blog, please visit our web site home page (www.realintent.com) or contact us for a consultation on how the Meridian CDC solution can make CDC signoff a reality.

Mar 26, 2010