Early Verification Products
- Ascent Lint
Automatic RTL Structural Verification
- Ascent AutoFormal
Automatic RTL Functional Verification
- Ascent XV
X-Propagation Management Tool
Advanced Sign-off Verification Products
- Meridian CDC
Clock Domain Crossing Sign-off Solution for RTL
- Meridian RDC
Reset Domain Crossing Sign-off Solution for RTL
- Meridian Constraints
Comprehensive SDC Management and Verification
- Meridian Physical CDC
Crossing Glitch Verification for Netlist
Design Intent Debug and Data Management
Meridian RDC is the fastest and most precise reset domain crossing sign-off tool on the
market. It performs comprehensive static analysis to ensure that signals crossing reset domains
function reliably. Among other things, Meridian RDC identifies metastability problems arising
from software and/or low power resets. Meridian RDC is the only solution that enables
comprehensive reset domain crossing sign-off.
RDC Chip-killer Bugs
Poor reset architecture and/or design can result in unreliable functional resets, causing intermittent catastrophic chip failures. As shown in Figure 1, static timing analysis (STA) constrains normal timing paths (shown in blue). But, if SOFT_RST-A asserts, while SOFT_RST-B does not assert, an untimed path is created through the reset port (shown in red). This may result in intermittent unpredictable silicon behavior.
These chip-killer errors are not caught in static solutions like STA, clock domain crossing (CDC) tools, or through simulation. They result in chip failures in the field that are difficult to diagnose and expensive to fix.
Reset functionality may be incorrect due to metastability, glitches on asynchronous resets, or reconvergence of synchronized resets. Metastability may result at a reset domain crossing when an asynchronous reset is asserted/deasserted. Glitches may cause spurious resets when an asynchronous reset is generated by combinatorial logic. Functional
loss of correlation of synchronized resets may result from reconvergence.
Precise RDC Sign-off
Meridian RDC is the only solution in the industry that automatically extracts resets and reset
domains and performs precise RDC analysis. Meridian RDC’s unique technology allows designers
to use effective strategies to guarantee complete RDC correctness. It verifies:
- Asynchronous resets that are crossing reset domains will not cause metastability
when resets are activated or de-activated
- Reconverging synchronized resets are functionally correlated
- Asynchronous resets are glitch-free
This provides best-in-class quality of results for reset integrity in the market.
High Performance and Capacity
Meridian RDC is built upon the proven, highest capacity, most comprehensive static analysis engines leveraged from market-leading Meridian CDC.
RDC can be performed on blocks, IPs, subsystems, or full-chip levels.
Smart Reporting and Powerful GUI
Meridian RDC’s smart reporting keeps users focused on important issues through efficient organization of findings. Helpful guidance and suggested actions help users pinpoint the source of the problems quickly. Real Intent’s state-of-the-art design intent debugger and analysis manager—iDebug—provides for user configurability and programmability with its command line interface (CLI). All the RDC analysis data is stored in a database that can be accessed through the CLI. Users can customize the debug methodology to match their design flows using spreadsheet reports, graphical reports, scripting, and so on.
Meridian RDC supports an integrated visualization tool. Pruned schematic views focus on fault-related logic, and with a few mouse clicks, users are directed to the RTL source code that caused the problem. This debug approach allows for easy investigation deep into the design to isolate the root cause for any warnings and errors.
- Automatic design environment capture from designs or SDC constraints
- Comprehensive clock and reset inference with automated setup checks ensure the integrity of results
- Detection and reporting of safe crossings
- Low noise metastability checking on unsafe crossings when resets are activated and de-activated
- Optional suppression of CDC issues minimizes duplication across tools>
- Ensures asynchronous resets are glitch-free
- Ensures functional correlation of synchronized resets
- Annotated schematics, waveforms, and links to the source using iVision simplify debug
- Debug flow and status tracking is facilitated with iDebug GUI and CLI
- Sign-off of resets w.r.t. metastability issues, glitch issues, and functional correlation of synchronized resets ensures predictable chip functionality
- Leverages proven CDC engines and flow for reliable results and easy adoption
- Enables RDC verification on giga-gate SoC designs
- Fast performance for quick verification turnaround
- Precise non-overlapping RDC reporting using integrated analysis minimizes the debug cycle.
Fast run times, accuracy, and ease of use make the Meridian RDC solution the best in the industry for comprehensive reset sign-off.