Meridian Constraints (PureTime)

Benefits:

Completeness and correctness validation of all constraints ( SDC /TCL) against the design source
Equivalency checking of two versions of constraints for a single design, or top vs. block assures consistency
Coverage analysis of constraints with incremental generation capability for in-complete constraints
False path and multi-cycle path verification using state of the art formal verifica-tion engines
Highest performance for quick verification turnaround
Eliminates incorrect timing exceptions that can mask silicon timing failure
Protects against glitches on timing exceptions
Easily integrates with Real Intent’s tools and plugs straight into standard EDA flows

Features:

RTL as well as gate-level constraint management tasks
Constraints template generation with incremental capability from a seed SDC
Smart constraints check rules with precise reporting and debugging
Accurate path-level verification and reporting of exceptions
High performance combinational and sequential formal verification engines
Fast and powerful debugging capability with cross probing to TCL/SDC, schematic, and design source

Meridian Constraints (PureTime) Data Sheet:

English